UPSTREAM: nb/intel/945gc: Hardcode the integrated graphic frequencies

The code to set the igd frequencies is written with the mobile version
of the 945 chipset in mind and seems to cause cause strange igd
related problems on the desktop versions.

Some possible problems are:
* on 800MHz fsb CPUs the igd sometimes has artifacts on the screen;
* on 800MHz fsb CPU memtest results vary a lot;
* since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using
  variant board scheme" that does not affect this northbridge, the
  display shows garbage as soon as Linux (4.8) modesets the display.

A fix is to hardcode the core display and render clocks to their
maximum, potentially also improving graphical performance.
Vendor bios on all boards in coreboot with this northbridge have the
same value in this PCI config address.

TESTED on P5GC-MX (display works fine again in Linux) and
user reports of it making GA-945GCM-S2L run more stable.

BUG=none
BRANCH=none
TEST=none

Change-Id: I47a2d4b2a12981d8c644108499230bc92769f1f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1853781748
Original-Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17981
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427477
This commit is contained in:
Arthur Heymans 2016-12-28 21:20:45 +01:00 committed by chrome-bot
commit 6293836970

View file

@ -3116,8 +3116,14 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
/* Program PLL settings */
sdram_program_pll_settings(&sysinfo);
/* Program Graphics Frequency */
sdram_program_graphics_frequency(&sysinfo);
/*
* Program Graphics Frequency
* Set core display and render clock on 945GC to the max
*/
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
sdram_program_graphics_frequency(&sysinfo);
else
pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
/* Program System Memory Frequency */
sdram_program_memory_frequency(&sysinfo);