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Support for gigabit ga-6vxc

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This commit is contained in:
Ronald G. Minnich 2000-11-02 03:34:10 +00:00
commit 620dff9ebb
4 changed files with 714 additions and 0 deletions
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190
src/mainboard/gigabit/ga-6bxc/crt0.S Normal file
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/*
* $ $
*
*/
#include <asm.h>
#include <intel.h>
#include <pciconf.h>
/*
* This is the entry code (the mkrom(8) utility makes a jumpvector
* to this adddess.
*
* When we get here we are in x86 real mode.
*
* %cs = 0xf000 %ip = 0x0000
* %ds = 0x0000 %es = 0x0000
* %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6,
* where x is undefined)
* %fl = 0x0002
*/
.text
.code16
/*
* Putting any code before the gdt tables breaks things
* because the lgdt instruction is hand assembled/hard coded.
*/
#include <cpu/p5/start32.inc>
jmp 1f
/* ========================================================== */
separator: .string "\r\n============================================\r\n"
greeting: .string "ISR Packbot BIOS.\r\n"
#include "date.h"
date: .string DATE
done: .string "done.\r\n"
initram: .string "Initializing SDRAM..."
initdata: .string "Initializing DATA, clearing BSS and STACK..."
jumpmain: .string "Jumping to intel_main()..."
delaytest: .string "Delay test... "
/* ========================================================== */
1:
intel_chip_post_macro(0x02)
#if defined(ITE_SUPER_IO)
#include <superio/ITE/it8671f/superio.inc>
#elif defined(SMC_SUPER_IO)
#include <superio/SMC/fdc37n769/superio.inc>
#endif
intel_chip_post_macro(0x03)
#ifdef SERIAL_CONSOLE
#include <pc80/serial.inc>
#endif
#include <ram/ramtest.inc>
intel_chip_post_macro(0x04)
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($separator)
TTYS0_TX_STRING($greeting)
TTYS0_TX_STRING($date)
TTYS0_TX_CHAR($'\n')
#endif
intel_chip_post_macro(0x05)
/* initialize the RAM */
/* different for each motherboard */
#include <northbridge/intel/440bx/raminit.inc>
intel_chip_post_macro(0x20)
#include <cpu/p6/earlymtrr.inc>
intel_chip_post_macro(0x21)
mov $0x00000000, %eax
mov $0x0009ffff, %ebx
mov $16, %ecx
CALLSP(ramtest)
intel_chip_post_macro(0x23)
cmp $16, %ecx
je 1f
intel_chip_post_macro(0x24)
jmp .Lhlt
1:
intel_chip_post_macro(0x25)
/* Figure out how much RAM is configured */
CS_READ($0x67)
mov $0, %ebx
mov %al, %bl
shl $23, %ebx
sub $1, %ebx
mov $0x00100000, %eax
mov $16, %ecx
CALLSP(ramtest)
intel_chip_post_macro(0x26)
cmp $16, %ecx
je 1f
intel_chip_post_macro(0x27)
jmp .Lhlt
1:
intel_chip_post_macro(0x30)
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($initdata)
#endif
/*
* Copy data into RAM and clear the BSS. Since these segments
* isn't really that big we just copy/clear using bytes, not
* double words.
*/
cld /* clear direction flag */
leal EXT(_ldata), %esi
leal EXT(_data), %edi
movl $EXT(_eldata), %ecx
subl %esi, %ecx
jz .Lnodata /* should not happen */
rep
movsb
.Lnodata:
intel_chip_post_macro(0x31)
/** clear stack */
xorl %edi, %edi
movl $_PDATABASE, %ecx
xorl %eax, %eax
rep
stosb
/** clear bss */
leal EXT(_bss), %edi
movl $EXT(_ebss), %ecx
subl %edi, %ecx
jz .Lnobss
xorl %eax, %eax
rep
stosb
.Lnobss:
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($done)
#endif
intel_chip_post_macro(0x3f)
/*
* Now we are finished. Memory is up, data is copied and
* bss is cleared. Now we call the ``main´´ routine and
* let it do the rest.
*/
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($jumpmain)
#endif
/* memory is up. Let's do the rest in C -- much easier. */
/* set new stack */
movl $_PDATABASE, %esp
call EXT(intel_main)
/*NOTREACHED*/
.Lhlt: hlt
jmp .Lhlt

163
src/mainboard/gigabit/ga-6bxc/irq_tables.c Normal file
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#include <subr.h>
/*
* This table must be located between 0x000f0000 and 0x000fffff.
* By defining it as a const it gets located in the code segment
* and therefore inside the necessary 64K block. -tds
*/
#define USB_DEVFN (PIIX4_DEVFN+2)
#define SUM_REST 0x00 /* ...just happens to be 0 */
#define CHECKSUM (0x00-(SUM_REST+PIIX4_DEVFN+USB_DEVFN))
// In spite of the comment below I have located this in the
// gigabit tree until we work this all out -- RGM
/*
* This table should work for most systems using the PIIX4
* southbridge that have 4 PCI slots.
*
* I recall that the 440GX board that Ron was using had
* the PIIX4 at a different location. This will effect the
* devfn of the router and USB controller as well as the
* checksum. Hopefully the defines will allow this to
* be a bit more portable.
* -tds
*/
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*5, /* u16 size - size of entire table struct */
0, /* u8 rtr_bus - router bus */
PIIX4_DEVFN, /* u8 rtr_devfn - router devfn */
0x0e00, /* u16 exclusive_irqs - mask of IRQs for PCI use */
0x8086, /* u16 rtr_vendor - router vendor id */
0x7110, /* u16 rtr_devfn - router device id */
0, /* u8 miniport_data - "crap" */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
/* struct irq_info slots[0] */
{
{
0, /* u8 bus */
USB_DEVFN, /* u8 devfn for USB controller */
{
{
0x00, /* u8 link - IRQ line ID */
0x0000, /* u16 bitmap - Available IRQs */
},
{
0x00, /* u8 link - IRQ line ID */
0x0000, /* u16 bitmap - Available IRQs */
},
{
0x00, /* u8 link - IRQ line ID */
0x0000, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
0, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x40, /* u8 devfn for PCI slot 1 */
{
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
1, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x48, /* u8 devfn for PCI slot 2 */
{
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
2, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x50, /* u8 devfn for PCI slot 3 */
{
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
3, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x58, /* u8 devfn for PCI slot 4 */
{
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
4, /* u8 slot */
0, /* u8 rfu */
}
}
};

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src/mainboard/gigabit/ga-6bxc/ldscript.ld Normal file
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/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*
* $Id$
*
*/
/* oh, barf. This won't work if all you use is .o's. -- RGM */
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
/*
* Memory map:
*
* 0x00000 (4*4096 bytes) : stack
* 0x04000 (4096 bytes) : private data
* 0x05000 : data space
* 0x90000 : kernel stack
* 0xf0000 (64 Kbyte) : EPROM
*/
MEMORY
{
ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is
* max for STPC */
rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
}
_PDATABASE = 0x04000;
_RAMBASE = 0x05000;
_KERNSTK = 0x90000;
/* should be parameterized but is not, yuck! */
/*
_ROMBASE = 0xe0000;
*/
_ROMBASE = 0xf0000;
/*
* Entry point is not really nececary, since the mkrom(8)
* tool creates a entry point that jumps to $0xc000:0x0000.
*/
/* baloney, but ... RGM*/
ENTRY(_start)
SECTIONS {
/*
* First we place the code and read only data (typically const declared).
* This get placed in rom.
*/
.text _ROMBASE : {
_text = .;
*(.text);
*(.rodata);
_etext = .;
}
_pdata = .;
/*
.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
SIZEOF(.rodata)) {
*/
.pdata _PDATABASE : AT ( _etext ) {
*(.pdata);
}
_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
/*
* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
* whereas __data_loadstart and __data_loadend shows where in rom to
* copy from.
*/
.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
_data = .;
*(.data)
*(.sdata)
*(.sdata2)
*(.got)
_edata = .;
}
_ldata = LOADADDR(.data);
_eldata = LOADADDR(.data) + SIZEOF(.data);
/*
* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between __bss_start and __bss_end with zeroes.
*/
.bss ( ADDR(.data) + SIZEOF(.data) ) : {
_bss = .;
*(.bss)
*(.sbss)
*(COMMON)
_ebss = .;
_heap = .;
}
}
/*
* This provides the start and end address for the whole image
*/
_image = LOADADDR(.text);
_eimage = LOADADDR(.data) + SIZEOF(.data);
/* EOF */