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UPSTREAM: src: change coreboot to lowercase

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The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

BUG=none
BRANCH=none
TEST=none

Change-Id: I280a7abeada01b4d158b2d65c3b59f1b98b81ad9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e18e6427d0
Original-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20029
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528259
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Martin Roth 2017-06-03 20:03:18 -06:00 • committed by chrome-bot
commit 61e8fe9239
35 changed files with 37 additions and 37 deletions
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2
src/vendorcode/amd/cimx/sb700/SBCMN.c
View file

@ -145,7 +145,7 @@ void commonInitEarlyBoot(AMDSBCFG* pConfig) {
RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
#if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
#if 0 //KZ [083011]-It's used wrong BIOS SIZE for coreboot.
//For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
//changing it.
ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);

2
src/vendorcode/amd/cimx/sb700/SBPort.c
View file

@ -222,7 +222,7 @@ void sbPowerOnInit (AMDSBCFG *pConfig){
if (dbVar0 > 4) {
dbVar0 = 0;
}
//KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
//KZ [061811]-It's used wrong BIOS SIZE for coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
if (pConfig->Spi33Mhz)
//spi reg0c[13:12] to 01h to run spi 33Mhz in system bios