UPSTREAM: src: change coreboot to lowercase

The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

BUG=none
BRANCH=none
TEST=none

Change-Id: I280a7abeada01b4d158b2d65c3b59f1b98b81ad9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e18e6427d0
Original-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20029
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528259
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>

src/cpu/amd/car/cache_as_ram.inc

@@ -45,7 +45,7 @@
  *   xmm2: Fam10h comparison value
  *   xmm3: Fam15h comparison value
  *   xmm4: Backup EBX
- *   xmm5: Coreboot init detect
+ *   xmm5: coreboot init detect
  */
 
 	/* Save the BIST result. */

src/cpu/amd/family_10h-family_15h/fidvid.c

@@ -60,7 +60,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
     by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
     if the warm reset is issued by coreboot to update NbFid. So it is required
     or not ? How can I tell who issued warm reset ?
-    Coreboot transitions to P0 instead, which is not recommended, and does
+    coreboot transitions to P0 instead, which is not recommended, and does
     not follow 2.4.2.15.2 to do so.
 
 9.- TODO Requires information on current delivery capability

src/cpu/amd/quadcore/quadcore_id.c

@@ -105,7 +105,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 		}
 	}
 	if (fam15h && dual_node) {
-		/* Coreboot expects each separate processor die to be on a different nodeid.
+		/* coreboot expects each separate processor die to be on a different nodeid.
 		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
 		 */
 		uint32_t f5x84;
@@ -123,7 +123,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 			id.coreid = id.coreid - core_count;
 		}
 	} else if (rev_gte_d && dual_node) {
-		/* Coreboot expects each separate processor die to be on a different nodeid.
+		/* coreboot expects each separate processor die to be on a different nodeid.
 		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
 		 */
 		uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1;