From 61af2899641fef2206c4d02db94fe98fec560cbe Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Wed, 15 Jun 2016 06:07:55 +0300
Subject: [PATCH] UPSTREAM: Fix some cbmem.h includes

Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15196
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit 465eff61f4f0f730476aa7afe8819f1e6b118068)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354181
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
---
 src/cpu/intel/haswell/cache_as_ram.inc               | 1 -
 src/cpu/intel/haswell/romstage.c                     | 2 +-
 src/cpu/intel/model_2065x/cache_as_ram.inc           | 1 -
 src/drivers/intel/fsp1_0/cache_as_ram.inc            | 1 -
 src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 1 -
 src/soc/intel/baytrail/romstage/cache_as_ram.inc     | 1 -
 src/soc/intel/broadwell/romstage/cache_as_ram.inc    | 1 -
 7 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index ddbffbbc60..e09e74b6c2 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -17,7 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 /* The full cache-as-ram size includes the cache-as-ram portion from coreboot
  * and the space used by the reference code. These 2 values combined should
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9932a508e5..9c08aa16ba 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/stages.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
-#include <cbfs.h>
+#include <cbmem.h>
 #include <romstage_handoff.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 6fa3eb82b5..269fbeffc7 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -17,7 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
index e79c3c19a6..189b4b2e3c 100644
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -18,7 +18,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 	cmp   $0, %eax
 	je    cache_as_ram
diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
index fcd2d3bce7..7349af85e6 100644
--- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
@@ -17,7 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 #define CACHE_AS_RAM_SIZE 0x10000
 #define CACHE_AS_RAM_BASE 0xd0000
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index 46bcc0356f..4a1d31f6da 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -17,7 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 #include "fmap_config.h"
 
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index aebdd83dab..a636e9f7ad 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -18,7 +18,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 /* The full cache-as-ram size includes the cache-as-ram portion from coreboot
  * and the space used by the reference code. These 2 values combined should