diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 96f9a936b5..0db0b14036 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -758,6 +758,19 @@ struct soc_intel_pantherlake_config {
 
 	/* Disable the progress bar during MRC training operations. */
 	bool disable_progress_bar;
+
+	/*
+	 * VgaInitControl CD Clock Frequency Selection
+	 * 0: CD_CLK_NONE - No higher CD Clock required
+	 * 1: CD_CLK_442MHZ - 441 MHz
+	 * 2: CD_CLK_461MHZ - 461 MHz
+	 */
+	enum cd_clock {
+		CD_CLK_NONE = 0,
+		CD_CLK_442MHZ,
+		CD_CLK_461MHZ,
+		MAX_CD_CLOCK = CD_CLK_461MHZ
+	} vga_cd_clk_freq_sel;
 };
 
 typedef struct soc_intel_pantherlake_config config_t;
diff --git a/src/soc/intel/pantherlake/romstage/ux.c b/src/soc/intel/pantherlake/romstage/ux.c
index e0a84257dc..4f9519b6e8 100644
--- a/src/soc/intel/pantherlake/romstage/ux.c
+++ b/src/soc/intel/pantherlake/romstage/ux.c
@@ -50,6 +50,17 @@ static void setup_vga_mode12_params(FSP_M_CONFIG *m_cfg, enum ux_locale_msg id)
 		m_cfg->VgaInitControl |= VGA_INIT_CONTROL_MODE12_MONOCHROME;
 }
 
+static void set_cd_clock(FSP_M_CONFIG *m_cfg, enum cd_clock clk)
+{
+	if (clk > MAX_CD_CLOCK) {
+		printk(BIOS_ERR, "CD Clock setting out of bounds!\n");
+		return;
+	}
+
+	m_cfg->VgaInitControl = (m_cfg->VgaInitControl & ~(0x3 << 6)) | (clk << 6);
+	printk(BIOS_DEBUG, "CD Clock: %d\n", clk);
+}
+
 static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 		 FSPM_UPD *mupd)
 {
@@ -90,6 +101,9 @@ static bool ux_inform_user_of_operation(const char *name, enum ux_locale_msg id,
 	m_cfg->VgaInitControl = VGA_INIT_CONTROL_ENABLE;
 	if (config->disable_progress_bar)
 		m_cfg->VgaInitControl |= VGA_INIT_DISABLE_ANIMATION;
+
+	set_cd_clock(m_cfg, config->vga_cd_clk_freq_sel);
+
 	m_cfg->VbtPtr = (efi_uintn_t)vbt;
 	m_cfg->VbtSize = vbt_size;
 	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);