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UPSTREAM: intel/fsp_baytrail: Always log PcdEnableLpe and PcdeMMCBootMode

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Log the values of PcdEnableLpe and PcdeMMCBootMode even if they are
outside of the expected range.

TEST=Intel/MinnowMax

BUG=None
BRANCH=None

Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: https://review.coreboot.org/10164
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ie0aea4287234b23d4e9852f3991dcc78ce8103d9
Reviewed-on: https://chromium-review.googlesource.com/412418
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
David Imhoff 2015-05-10 15:15:25 +02:00 • committed by chrome-bot
commit 6123f7845b
1 changed files with 7 additions and 0 deletions
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7
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
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@ -209,10 +209,17 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
if (UpdData->PcdEnableLpe < sizeof(acpi_pci_mode_strings) / sizeof (char *))
printk(FSP_INFO_LEVEL, "Lpe:\t\t\t%s\n",
acpi_pci_mode_strings[UpdData->PcdEnableLpe]);
else
printk(FSP_INFO_LEVEL, "Lpe:\t\t\tUnknown (0x%02x)\n",
UpdData->PcdEnableLpe);
if (UpdData->PcdeMMCBootMode < sizeof(emmc_mode_strings) / sizeof (char *))
printk(FSP_INFO_LEVEL, "eMMC Mode:\t\t%s\n",
emmc_mode_strings[UpdData->PcdeMMCBootMode]);
else
printk(FSP_INFO_LEVEL, "eMMC Mode:\t\tUnknown (0x%02x)\n",
UpdData->PcdeMMCBootMode);
if (UpdData->PcdEnableSata)
printk(FSP_INFO_LEVEL, "SATA Mode:\t\t%s\n",