nb/via/cx700: Implement FSB tuning
This northbridge provides a lot of knobs for fine-grained tuning of the FSB drivers. The programming manual calls this "Host AGTL+ I/O Driving Control". We program the known good values for use with a VIA C7 CPU, and warn about use with different CPUs. The numbers were pulled out of raminit of the original CX700 port. Originally, there was a write to 0x83 as well, to set bit 1 which triggers a soft reset of the CPU. It was amidst a table, so it seems unclear if it was put there intentionally. Change-Id: I24ba6cfaab2ca3069952a6c399a065caea7b49f2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stddef.h>
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#include <stdint.h>
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#include <commonlib/bsd/helpers.h>
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#include <device/pci_ops.h>
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#include <static_devices.h>
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#include <romstage_common.h>
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#include <halt.h>
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static void tune_fsb(void)
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{
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if (!CONFIG(CPU_VIA_C7)) {
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printk(BIOS_WARNING,
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"FSB settings are known for VIA C7 CPUs, P4 compat. is unknown.\n");
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}
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static const struct {
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uint8_t reg;
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uint8_t val;
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} fsb_settings[] = {
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{ 0x70, 0x33 },
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{ 0x71, 0x11 },
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{ 0x72, 0x33 },
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{ 0x73, 0x11 },
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{ 0x74, 0x20 },
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{ 0x75, 0x2e },
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{ 0x76, 0x64 },
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{ 0x77, 0x00 },
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{ 0x78, 0x44 },
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{ 0x79, 0xaa },
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{ 0x7a, 0x33 },
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{ 0x7b, 0xaa },
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{ 0x7c, 0x00 },
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{ 0x7e, 0x33 },
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{ 0x7f, 0x33 },
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{ 0x80, 0x44 },
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{ 0x81, 0x44 },
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{ 0x82, 0x44 },
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};
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for (size_t i = 0; i < ARRAY_SIZE(fsb_settings); ++i)
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pci_write_config8(_sdev_host_if, fsb_settings[i].reg, fsb_settings[i].val);
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}
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void __noreturn romstage_main(void)
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{
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/* Allows access to all northbridge PCI devfn's */
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pci_write_config8(_sdev_host_ctrl, 0x4f, 0x01);
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tune_fsb();
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/* Needed for __noreturn */
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halt();
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}
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