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UPSTREAM: soc/intel/skylake: Handle platform global reset

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In FSP1.1 all the platform resets including global was handled
on its own without any intervention from coreboot.
In FSP2.0, any reset required will be notified to coreboot
and it is expected that coreboot will perform platform reset.

Hence, implement platform global reset hooks in coreboot. If Intel
ME is in non ERROR state then MEI message will able to perform
global reset else force global reset by writing 0x6 or 0xE to
0xCF9 port with PCH ETR3 register bit [20] set.

BUG=none
BRANCH=none
TEST=Verified platform global reset is working with MEI
message or writing to PCH ETR3.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16903
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5
Reviewed-on: https://chromium-review.googlesource.com/400115
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2016-08-19 13:17:36 +05:30 • committed by chrome-bot
commit 5f9e1369fb
1 changed files with 34 additions and 1 deletions
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35
src/soc/intel/skylake/reset.c
View file

@ -16,13 +16,46 @@
#include <console/console.h>
#include <fsp/util.h>
#include <reset.h>
#include <soc/me.h>
#include <soc/pm.h>
#include <timer.h>
static void do_force_global_reset(void)
{
u32 reg32;
/*PMC Controller Device 0x1F, Func 02*/
uint8_t *pmc_regs;
/*
* BIOS should ensure it does a global reset
* to reset both host and Intel ME by setting
* PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
*/
pmc_regs = pmc_mmio_regs();
reg32 = read32(pmc_regs + ETR3);
reg32 |= ETR3_CF9GR;
write32(pmc_regs + ETR3, reg32);
/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
* to global reset platform */
hard_reset();
}
void global_reset(void)
{
if (send_global_reset() != 0) {
/* If ME unable to reset platform then
* force global reset using PMC CF9GR register*/
do_force_global_reset();
}
}
void chipset_handle_reset(uint32_t status)
{
switch(status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
hard_reset();
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);