diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h
index ffeb2f055a..2e16a322c5 100644
--- a/src/soc/intel/skylake/include/soc/me.h
+++ b/src/soc/intel/skylake/include/soc/me.h
@@ -3,6 +3,8 @@
 #ifndef _SKYLAKE_ME_H_
 #define _SKYLAKE_ME_H_
 
+#include <intelblocks/cse.h>
+
 /*
  * Management Engine PCI registers
  */
@@ -189,6 +191,6 @@ union me_hfsts6 {
 };
 
 void intel_me_status(void);
-int send_global_reset(void);
+enum cse_tx_rx_status send_global_reset(void);
 
 #endif
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index 89491f89c3..e91719f00c 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -338,9 +338,9 @@ void intel_me_status(void)
 	}
 }
 
-int send_global_reset(void)
+enum cse_tx_rx_status send_global_reset(void)
 {
-	int status = 0;
+	enum cse_tx_rx_status status = CSE_TX_ERR_CSE_NOT_READY;
 	union me_hfsts1 hfs1;
 
 	if (!is_cse_enabled())
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 8bf9db5830..3ef5f09354 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -22,7 +22,7 @@ static void do_force_global_reset(void)
 
 void do_global_reset(void)
 {
-	if (!send_global_reset()) {
+	if (send_global_reset() != CSE_TX_RX_SUCCESS) {
 		/* If ME unable to reset platform then
 		 * force global reset using PMC CF9GR register*/
 		do_force_global_reset();