UPSTREAM: AMD MTRR: Add common add_uma_resource_below_tolm()
BUG=none
BRANCH=none
TEST=none
Change-Id: I0510eb6bdbb7c2aa29bc882ee09088aad37b6a6e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 17bb225be7
Original-Change-Id: I9eee88dc619ac5d9c77153db522a6ead65f6c9b1
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19376
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/508777
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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2 changed files with 20 additions and 0 deletions
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@ -11,6 +11,7 @@
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/cpu.h>
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@ -76,6 +77,23 @@ static void setup_ap_ramtop(void)
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wrmsr(TOP_MEM2, msr);
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}
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void add_uma_resource_below_tolm(struct device *nb, int idx)
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{
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uint32_t topmem = bsp_topmem();
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uint32_t top_of_cacheable = get_top_of_ram();
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if (top_of_cacheable == topmem)
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return;
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uint32_t uma_base = top_of_cacheable;
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uint32_t uma_size = topmem - top_of_cacheable;
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printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
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__func__, uma_size, uma_base);
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uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
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}
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void amd_setup_mtrrs(void)
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{
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unsigned long address_bits;
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@ -41,6 +41,8 @@
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#include <cpu/x86/msr.h>
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void amd_setup_mtrrs(void);
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struct device;
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void add_uma_resource_below_tolm(struct device *nb, int idx);
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static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
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{
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