UPSTREAM: AMD MTRR: Add common add_uma_resource_below_tolm()

BUG=none
BRANCH=none
TEST=none

Change-Id: I0510eb6bdbb7c2aa29bc882ee09088aad37b6a6e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 17bb225be7
Original-Change-Id: I9eee88dc619ac5d9c77153db522a6ead65f6c9b1
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19376
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/508777
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-04-19 19:55:54 +03:00 committed by chrome-bot
commit 5e50cfa854
2 changed files with 20 additions and 0 deletions

View file

@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/cpu.h>
@ -76,6 +77,23 @@ static void setup_ap_ramtop(void)
wrmsr(TOP_MEM2, msr);
}
void add_uma_resource_below_tolm(struct device *nb, int idx)
{
uint32_t topmem = bsp_topmem();
uint32_t top_of_cacheable = get_top_of_ram();
if (top_of_cacheable == topmem)
return;
uint32_t uma_base = top_of_cacheable;
uint32_t uma_size = topmem - top_of_cacheable;
printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
__func__, uma_size, uma_base);
uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
}
void amd_setup_mtrrs(void)
{
unsigned long address_bits;

View file

@ -41,6 +41,8 @@
#include <cpu/x86/msr.h>
void amd_setup_mtrrs(void);
struct device;
void add_uma_resource_below_tolm(struct device *nb, int idx);
static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
{