This patch adds CAR support for LX, as well as the include file. It
builds but is not tested. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@323 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Stefan Reinauer
parent
42b209a0be
commit
5dfd441cdf
2 changed files with 973 additions and 0 deletions
411
arch/x86/stage0_amd_geodelx.S
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411
arch/x86/stage0_amd_geodelx.S
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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##
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## Copyright (C) 2005 Eswar Nallusamy, LANL
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##
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## Copyright (C) 2005 Tyan
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## Written by Yinghai Lu <yhlu@tyan.com> for Tyan.
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##
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## Copyright (C) 2007 coresystems GmbH
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## Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH.
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##
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## Copyright (C) 2007 Advanced Micro Devices
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# init code - switch cpu to pmode and enable cache as ram.
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#include "macros.h"
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#include <amd_geodelx.h>
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#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
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#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-4)
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#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
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#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
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#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
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#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
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#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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.code16
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.globl _stage0
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_stage0:
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cli
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/* save the BIST result */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.com.tw for this TLB fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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* didn't invalidate it.
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB */
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/* switch to protected mode */
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/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
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* using BFD version 2.15.94.0.2.2 20041220 this works fine without all
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* the ld hackery and other things. So leave it as is with this comment.
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*/
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data32 lgdt %cs:gdtptr
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Restore BIST result */
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movl %ebp, %eax
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// port80_post (0x23) /* post 0x01 */
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/* Now we are in protected mode. Jump to a 32 bit code segment. */
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data32 ljmp $ROM_CODE_SEG, $protected_stage0
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/* I am leaving this weird jump in here in the event that future gas bugs force it to be used. */
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#.byte 0x66
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.code32
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#ljmp $ROM_CODE_SEG, $protected_stage0
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#.code16
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.align 4
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.globl gdt16
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gdt16 = . - _stage0
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gdt16x:
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.word gdt16xend - gdt16x -1 /* compute the table limit */
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.long gdt16x
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt16xend:
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/* From now on we are 32bit */
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.code32
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/* We have two gdts where we could have one. That is ok.
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*
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* Let's not worry about this -- optimizing gdt is pointless since we're
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* only in it for a little bit.
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*
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* BTW note the trick below: The GDT points to ITSELF, and the first good
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* descriptor is at offset 8. So you word-align the table, and then because
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* you chose 8, you get a nice 64-bit aligned GDT entry, which is good as
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* this is the size of the entry.
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* Just in case you ever wonder why people do this.
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*/
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.align 4
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.globl gdtptr
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.globl gdt_limit
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gdt_limit = gdt_end - gdt - 1 /* compute the table limit */
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gdt:
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gdtptr:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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/* selgdt 0x18, flat code segment for CAR */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x20,flat data segment for CAR */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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.globl protected_stage0
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protected_stage0:
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//This code was used by v2. TODO
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_stage0
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.globl __protected_stage0
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__protected_stage0:
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/* Save the BIST value */
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movl %eax, %ebp
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port80_post (0x01) /* post 0x01 */
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax */
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movl %ebp, %eax
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.align 4
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/* here begins CAR support */
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/* this particular code is straight from LinuxBIOS V2 */
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/***************************************************************************
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/**
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/** DCacheSetup
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/**
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/** Setup data cache for use as RAM for a stack.
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/**
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/***************************************************************************/
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DCacheSetup:
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invd
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/* set cache properties */
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movl $CPU_RCONF_DEFAULT, %ecx
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rdmsr
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movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */
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wrmsr
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/* in LX DCDIS is set after POR which disables the cache..., clear this bit */
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movl CPU_DM_CONFIG0,%ecx
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rdmsr
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andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */
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wrmsr
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/* get cache timing params from BIOS config data locations and apply */
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/* fix delay controls for DM and IM arrays */
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/* fix delay controls for DM and IM arrays */
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movl $CPU_BC_MSS_ARRAY_CTL0, %ecx
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xorl %edx, %edx
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movl $0x2814D352, %eax
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wrmsr
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movl $CPU_BC_MSS_ARRAY_CTL1, %ecx
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xorl %edx, %edx
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movl $0x1068334D, %eax
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wrmsr
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movl $CPU_BC_MSS_ARRAY_CTL2, %ecx
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movl $0x00000106, %edx
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movl $0x83104104, %eax
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wrmsr
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movl $GLCP_FIFOCTL, %ecx
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rdmsr
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movl $0x00000005, %edx
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wrmsr
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/* Enable setting */
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movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
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xorl %edx, %edx
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movl $0x01, %eax
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wrmsr
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/* Get cleaned up. */
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xorl %edi, %edi
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xorl %esi, %esi
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xorl %ebp, %ebp
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/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
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/* remember, there is NO stack yet... */
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/* Tell cache we want to fill WAY 0 starting at the top */
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xorl %edx, %edx
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xorl %eax, %eax
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movl $CPU_DC_INDEX, %ecx
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wrmsr
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/* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
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movl $LX_STACK_BASE, %ebp /* init to start address */
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orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
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/* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
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movl $LX_NUM_CACHELINES, %edi
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DCacheSetupFillWay:
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/* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
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/* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
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movw $0x04, %si
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xorl %edx, %edx
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xorl %eax, %eax
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movl $CPU_DC_DATA, %ecx
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DCacheSetup_quadWordLoop:
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wrmsr
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decw %si
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jnz DCacheSetup_quadWordLoop
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/* Set the tag for this line, need to do this for every new cache line to validate it! */
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/* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
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xorl %edx, %edx
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movl %ebp, %eax
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movl $CPU_DC_TAG, %ecx
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wrmsr
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/* switch to next line */
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/* lines are in Bits10:4 */
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/* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */
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movl $CPU_DC_INDEX, %ecx
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rdmsr
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addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
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wrmsr
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decl %edi
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jnz DCacheSetupFillWay
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/* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */
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addl $LX_CACHEWAY_SIZE, %ebp
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cmpl $LX_STACK_END, %ebp
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jge leave_DCacheSetup
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movl $LX_NUM_CACHELINES, %edi
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/* switch to next way */
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movl $CPU_DC_INDEX, %ecx
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rdmsr
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addl $0x01, %eax
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andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
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wrmsr
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jmp DCacheSetupFillWay
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leave_DCacheSetup:
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xorl %edi, %edi
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xorl %esi, %esi
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xorl %ebp, %ebp
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/* Disable the cache, but ... DO NOT INVALIDATE the tags. */
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/* Memory reads and writes will all hit in the cache. */
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/* Cache updates and memory write-backs will not occur ! */
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movl %cr0, %eax
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orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */
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movl %eax, %cr0
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/* Now point sp to the cached stack. */
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/* The stack will be fully functional at this location. No system memory is required at all ! */
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/* set up the stack pointer */
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movl $LX_STACK_END, %eax
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movl %eax, %esp
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/* test the stack*/
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movl $0x0F0F05A5A, %edx
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pushl %edx
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popl %ecx
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cmpl %ecx, %edx
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je DCacheSetupGood
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movb $0xC5, %al
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outb %al, $0x80
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DCacheSetupBad:
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hlt /* issues */
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jmp DCacheSetupBad
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DCacheSetupGood:
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/* If you wanted to maintain the stack in memory you would need to set the tags as dirty
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so the wbinvd would push out the old stack contents to memory */
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/* Clear the cache, the following code from crt0.S.lb will setup a new stack*/
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wbinvd
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/* at this point, CAR should be working */
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movl $(LX_STACK_END), %eax
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movl %eax, %esp
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/* Load a different set of data segments */
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movw $CACHE_RAM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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lout:
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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call stage1_main
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/* We will not go back */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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# Reset vector.
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/*
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RVECTOR: size of reset vector, default is 0x10
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RESRVED: size of vpd code, default is 0xf0
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BOOTBLK: size of bootblock code, default is 0x1f00 (8k-256b)
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*/
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SEGMENT_SIZE = 0x10000
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RVECTOR = 0x00010
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# Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
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# I think we should leave it this way forever, as the bugs come and
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# go -- and come again.
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# .code16
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# .section ".rom.text"
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.section ".reset", "ax"
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.globl _resetjump
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_resetjump:
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/* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
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# jmp _stage0
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.byte 0xe9
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.int _stage0 - ( . + 2 )
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/* Note: The above jump is hand coded to work around bugs in binutils.
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* 5 byte are used for a 3 byte instruction. This works because x86
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* is little endian and allows us to use supported 32bit relocations
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* instead of the weird 16 bit relocations that binutils does not
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* handle consistenly between versions because they are used so rarely.
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*/
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.byte 0
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# Date? ID string? We might want to put something else in here.
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.ascii DATE
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# Checksum.
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#.word 0
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Loading…
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Reference in a new issue