From 5daf497df4972c973b6a25602c5bea31b1988763 Mon Sep 17 00:00:00 2001
From: Ziang Wang <wangziang.ok@bytedance.com>
Date: Tue, 14 Oct 2025 15:14:26 +0800
Subject: [PATCH] arch/riscv: Add ACPI support for riscv

Add ACPI table creation routine for riscv. An empty header 'pci_ops.h'
is added to pass build.

TEST=Build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt,aia=aplic-imsic,acpi=on -bios
build/coreboot.rom -nographic -pflash build/coreboot.rom".

Change-Id: Ifa57bd8511e73c3406bcf2672fed90c1e86a4ffd
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
---
 src/arch/riscv/include/arch/pci_ops.h |  9 +++++++++
 src/arch/riscv/tables.c               | 21 +++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 src/arch/riscv/include/arch/pci_ops.h

diff --git a/src/arch/riscv/include/arch/pci_ops.h b/src/arch/riscv/include/arch/pci_ops.h
new file mode 100644
index 0000000000..25c4f82a72
--- /dev/null
+++ b/src/arch/riscv/include/arch/pci_ops.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef ARCH_RISCV_PCI_OPS_H
+#define ARCH_RISCV_PCI_OPS_H
+
+#include <device/pci_def.h>
+#include <device/pci_mmio_cfg.h>
+
+#endif
diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c
index 9fc75f455c..0ff238c59e 100644
--- a/src/arch/riscv/tables.c
+++ b/src/arch/riscv/tables.c
@@ -4,9 +4,30 @@
 #include <boot/tables.h>
 #include <boot/coreboot_tables.h>
 #include <symbols.h>
+#include <assert.h>
+#include <acpi/acpi.h>
+#include <cbmem.h>
+#include <console/console.h>
+
+unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current)
+{
+	return current;
+}
+
+static void write_acpi_table(void)
+{
+	const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB;
+	const uintptr_t acpi_start = (uintptr_t)cbmem_add(CBMEM_ID_ACPI, max_acpi_size);
+	assert(IS_ALIGNED(acpi_start, 16));
+	const uintptr_t acpi_end = write_acpi_tables(acpi_start);
+	assert(acpi_end < acpi_start + max_acpi_size);
+	printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", acpi_end - acpi_start);
+}
 
 void arch_write_tables(uintptr_t coreboot_table)
 {
+	if (CONFIG(HAVE_ACPI_TABLES))
+		write_acpi_table();
 }
 
 void bootmem_arch_add_ranges(void)