From 5c1a9fa809480215b792c67eb519dad1fafa56d5 Mon Sep 17 00:00:00 2001 From: Luca Lai Date: Wed, 24 Sep 2025 20:33:09 +0800 Subject: [PATCH] mb/google/fatcat: Create ruby variant Create the ruby variant of the fatcat reference board by copying the fatcat files to a new directory named for the variant. BUG=b:446771934 TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a make sure the build includes GOOGLE_RUBY 2. Run part_id_gen tool without any errors Change-Id: Ie5f4a152d792f241a0044f18653b5363e1637b49 Signed-off-by: Luca Lai Reviewed-on: https://review.coreboot.org/c/coreboot/+/89327 Reviewed-by: Kapil Porwal Reviewed-by: Bob Moragues Reviewed-by: Derek Huang Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/Kconfig | 14 + src/mainboard/google/fatcat/Kconfig.name | 3 + .../baseboard/fatcat/include/baseboard/gpio.h | 5 + .../google/fatcat/variants/ruby/Makefile.mk | 8 + .../google/fatcat/variants/ruby/fw_config.c | 28 ++ .../google/fatcat/variants/ruby/gpio.c | 440 ++++++++++++++++++ .../google/fatcat/variants/ruby/hda_verb.c | 126 +++++ .../fatcat/variants/ruby/include/variant/ec.h | 8 + .../variants/ruby/include/variant/gpio.h | 11 + .../google/fatcat/variants/ruby/memory.c | 100 ++++ .../fatcat/variants/ruby/memory/Makefile.mk | 7 + .../ruby/memory/dram_id.generated.txt | 7 + .../variants/ruby/memory/mem_parts_used.txt | 12 + .../fatcat/variants/ruby/overridetree.cb | 302 ++++++++++++ 14 files changed, 1071 insertions(+) create mode 100644 src/mainboard/google/fatcat/variants/ruby/Makefile.mk create mode 100644 src/mainboard/google/fatcat/variants/ruby/fw_config.c create mode 100644 src/mainboard/google/fatcat/variants/ruby/gpio.c create mode 100644 src/mainboard/google/fatcat/variants/ruby/hda_verb.c create mode 100644 src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h create mode 100644 src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory.c create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/fatcat/variants/ruby/overridetree.cb diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 3a54cc29e4..6d9c72a167 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -151,6 +151,16 @@ config BOARD_GOOGLE_MOONSTONE select HAVE_SLP_S0_GATE select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD +config BOARD_GOOGLE_MODEL_RUBY + def_bool n + select BOARD_GOOGLE_BASEBOARD_FATCAT + select FSP_UGOP_EARLY_SIGN_OF_LIFE + select HAVE_SLP_S0_GATE + select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD + +config BOARD_GOOGLE_RUBY + select BOARD_GOOGLE_MODEL_RUBY + if BOARD_GOOGLE_FATCAT_COMMON config BASEBOARD_DIR @@ -190,6 +200,7 @@ config DRIVER_TPM_I2C_BUS default 0x03 if BOARD_GOOGLE_MODEL_KINMEN default 0x03 if BOARD_GOOGLE_LAPIS default 0x03 if BOARD_GOOGLE_MOONSTONE + default 0x03 if BOARD_GOOGLE_MODEL_RUBY config HAVE_SLP_S0_GATE def_bool n @@ -208,6 +219,7 @@ config MAINBOARD_PART_NUMBER default "Kinmen" if BOARD_GOOGLE_MODEL_KINMEN default "Lapis" if BOARD_GOOGLE_LAPIS default "Moonstone" if BOARD_GOOGLE_MOONSTONE + default "Ruby" if BOARD_GOOGLE_MODEL_RUBY config MEMORY_SOLDERDOWN def_bool n @@ -222,6 +234,7 @@ config TPM_TIS_ACPI_INTERRUPT default 66 if BOARD_GOOGLE_MODEL_KINMEN # GPE0_DW2_02 (GPP_E02) default 66 if BOARD_GOOGLE_LAPIS # GPE0_DW2_02 (GPP_E02) default 66 if BOARD_GOOGLE_MOONSTONE # GPE0_DW2_02 (GPP_E02) + default 66 if BOARD_GOOGLE_MODEL_RUBY # GPE0_DW2_02 (GPP_E02) # FIXME: update as per board schematics config UART_FOR_CONSOLE @@ -239,6 +252,7 @@ config VARIANT_DIR default "kinmen" if BOARD_GOOGLE_MODEL_KINMEN default "lapis" if BOARD_GOOGLE_LAPIS default "moonstone" if BOARD_GOOGLE_MOONSTONE + default "ruby" if BOARD_GOOGLE_MODEL_RUBY config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name index 46b7158971..61582c5102 100644 --- a/src/mainboard/google/fatcat/Kconfig.name +++ b/src/mainboard/google/fatcat/Kconfig.name @@ -43,3 +43,6 @@ config BOARD_GOOGLE_LAPIS config BOARD_GOOGLE_MOONSTONE bool "-> Moonstone" + +config BOARD_GOOGLE_RUBY + bool "-> Ruby" diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index d3ec2fdb6f..88c8e0047d 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -47,6 +47,11 @@ #define GPIO_PCH_WP GPP_D02 /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_V17 +#elif CONFIG(BOARD_GOOGLE_RUBY) + #define EC_SYNC_IRQ GPP_E07_IRQ + #define GPIO_PCH_WP GPP_D02 +/* Used to gate SoC's SLP_S0# signal */ +#define GPIO_SLP_S0_GATE GPP_V17 #endif #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/ruby/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/Makefile.mk new file mode 100644 index 0000000000..6c0a1ae6fb --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +romstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/fatcat/variants/ruby/fw_config.c b/src/mainboard/google/fatcat/variants/ruby/fw_config.c new file mode 100644 index 0000000000..8c207ed5e2 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/fw_config.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* t: base table; o: override table */ +#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o)) +/* t: table */ +#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t)) + +void fw_config_configure_pre_mem_gpio(void) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); + return; + } +} + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); + return; + } +} diff --git a/src/mainboard/google/fatcat/variants/ruby/gpio.c b/src/mainboard/google/fatcat/variants/ruby/gpio.c new file mode 100644 index 0000000000..f17fc8a883 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/gpio.c @@ -0,0 +1,440 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* GPP_A00: ESPI_IO0_EC_R */ + /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */ + + /* GPP_A01: ESPI_IO1_EC_R */ + /* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */ + + /* GPP_A02: ESPI_IO2_EC_R */ + /* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */ + + /* GPP_A03: ESPI_IO3_EC_R */ + /* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */ + + /* GPP_A04: ESPI_CS0_EC_R_N */ + /* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */ + + /* GPP_A05: ESPI_CLK_EC_R */ + /* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */ + + /* GPP_A06: ESPI_RST_EC_R_N */ + /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ + + /* GPP_A08: NC */ + PAD_NC(GPP_A08, NONE), + /* GPP_A09: NC */ + PAD_NC(GPP_A09, NONE), + /* GPP_A10: NC */ + PAD_NC(GPP_A10, NONE), + /* GPP_A11: TP */ + PAD_NC(GPP_A11, NONE), + /* GPP_A12: NC */ + PAD_NC(GPP_A12, NONE), + /* GPP_A13: MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_A13, NONE, DEEP), + /* GPP_A15: SOC_GPP_A15 */ + PAD_CFG_GPI(GPP_A15, NONE, DEEP), + /* GPP_A16: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A16, 1, DEEP), + /* GPP_A17: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + + /* GPP_B00: USBC_SML_CLK_PD */ + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), + /* GPP_B01: USBC_SML_DATA_PD */ + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), + /* GPP_B02: NC */ + PAD_NC(GPP_B02, NONE), + /* GPP_B03: NC */ + PAD_NC(GPP_B03, NONE), + + /* GPP_B06: NC */ + PAD_NC(GPP_B06, NONE), + /* GPP_B07: NC */ + PAD_NC(GPP_B07, NONE), + /* GPP_B08: NC */ + PAD_NC(GPP_B08, NONE), + /* GPP_B09: M2_GEN4_SSD_RESET_N */ + PAD_CFG_GPO(GPP_B09, 1, PLTRST), + /* GPP_B10: NC */ + PAD_NC(GPP_B10, NONE), + /* GPP_B1: NC */ + PAD_NC(GPP_B11, NONE), + /* GPP_B12: PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14: MOD_TCSS2_DISP_HPD4 */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), + /* GPP_B15: NC */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16: GEN5_SSD_PWREN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + /* GPP_B17: NC */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), + /* GPP_B20: NC */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21: TCP_RETIMER_FORCE_PWR */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + /* GPP_B22: NC */ + PAD_NC(GPP_B22, NONE), + /* GPP_B24: MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_B24, NONE, DEEP), + /* GPP_B25: MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_B25, NONE, DEEP), + + /* GPP_C00: NC */ + PAD_NC(GPP_C00, NONE), + /* GPP_C01: NC */ + PAD_NC(GPP_C01, NONE), + /* GPP_C02: GPP_C2_STRAP */ + PAD_CFG_GPI(GPP_C02, NONE, DEEP), + /* GPP_C03: NC */ + PAD_NC(GPP_C03, NONE), + /* GPP_C04: NC */ + PAD_NC(GPP_C04, NONE), + PAD_CFG_GPO(GPP_C05, 1, DEEP), + /* GPP_C06: NC */ + PAD_NC(GPP_C06, NONE), + + /* GPP_C07: MEM_CH_SEL */ + PAD_CFG_GPI(GPP_C07, NONE, DEEP), + /* GPP_C08: NC */ + PAD_NC(GPP_C08, NONE), + /* GPP_C09: NC */ + PAD_NC(GPP_C09, NONE), + /* GPP_C10: NC */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11: NC */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12: NC */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13: NC */ + PAD_NC(GPP_C13, NONE), + /* GPP_C14: NC */ + PAD_NC(GPP_C14, NONE), + /* GPP_C16: TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17: TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18: NC */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19: NC */ + PAD_NC(GPP_C19, NONE), + /* GPP_C20: MOD_TCSS1_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21: MOD_TCSS1_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22: MOD_TCSS2_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: MOD_TCSS2_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + /* GPP_D00: TP */ + PAD_NC(GPP_D00, NONE), + /* GPP_D02: SOC_WP_OD */ + PAD_CFG_GPI(GPP_D02, NONE, DEEP), + /* GPP_D03: NC */ + PAD_NC(GPP_D03, NONE), + /* GPP_D04: TP */ + PAD_NC(GPP_D04, NONE), + /* GPP_D07: NC */ + PAD_NC(GPP_D07, NONE), + /* GPP_D08: NC */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09: I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* GPP_D10: HDA_BCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11: HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), + /* GPP_D12: HDA_SDO */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* GPP_D13: HDA_SDI0 */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D14: NC */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15: NC */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16: TP*/ + PAD_NC(GPP_D16, NONE), + /* GPP_D17: TP*/ + PAD_NC(GPP_D17, NONE), + /* GPP_D18: CLKREQ6_X4_GEN4_M2_SSD_N */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D19: NC */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20: CSE_EARLY_SW */ + PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL), + /* GPP_D21: NC */ + PAD_NC(GPP_D21, NONE), + /* GPP_D22: NC */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23: NC */ + PAD_NC(GPP_D23, NONE), + /* GPP_D24: MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_D24, NONE, DEEP), + /* GPP_D25: NC */ + PAD_NC(GPP_D25, NONE), + + /* GPP_E01: NC */ + PAD_NC(GPP_E01, NONE), + /* GPP_E02: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E03: NC */ + PAD_NC(GPP_E03, NONE), + /* GPP_E05: TCHSCR_RPT_EN */ + PAD_CFG_GPO(GPP_E05, 1, DEEP), + /* GPP_E06: SECURE_CAM_SW */ + PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI), + /* GPP_E07 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E08: NC */ + PAD_NC(GPP_E08, NONE), + /* GPP_E10: TP */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11: NC */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PAD1*/ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PAD1 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E14: NC */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: NC */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17: NC */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: TCHPAD_INT# */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E19: FPMCU_PWREN */ + PAD_CFG_GPO(GPP_E19, 1, DEEP), + /* GPP_E20: NC */ + PAD_NC(GPP_E20, NONE), + /* GPP_E21: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* GPP_E22: NC */ + PAD_NC(GPP_E22, NONE), + + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06: NC */ + PAD_NC(GPP_F06, NONE), + /* GPP_F07: NC */ + PAD_NC(GPP_F07, NONE), + /* GPP_F08: EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_F08, 1, DEEP), + /* GPP_F09: NC */ + PAD_NC(GPP_F09, NONE), + /* GPP_F10: ISH_GP_6_SNSR_HDR */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8), + /* GPP_F11: NC */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12: TCHSCR_I2C5_SCL */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), + /* GPP_F13: TCHSCR_I2C5_SDA */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), + /* GPP_F14: NC */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15: NC */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16: TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* GPP_F17: NC */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18: TCHSCR_INT_L */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), + /* GPP_F19: EN_UCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_F19, 0, PLTRST), + /* GPP_F20: NC */ + PAD_NC(GPP_F20, NONE), + /* GPP_F22: NC */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23: NC */ + PAD_NC(GPP_F23, NONE), + + /* GPP_H00: GPP_H0_STRAP */ + PAD_CFG_GPO(GPP_H00, 1, PLTRST), + /* GPP_H01: GPP_H1_STRAP */ + PAD_CFG_GPO(GPP_H01, 0, PLTRST), + /* GPP_H02: GPP_H2_STRAP */ + PAD_CFG_GPO(GPP_H02, 1, PLTRST), + /* GPP_H03: SOC_SPKR_INT_ODL */ + PAD_CFG_GPI(GPP_H03, NONE, DEEP), + /* GPP_H04: NC */ + PAD_NC(GPP_H04, NONE), + /* GPP_H05: NC */ + PAD_NC(GPP_H05, NONE), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: UART0_BUF_RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART0_BUF_TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10: NC */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11: NC */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13: CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14: NC */ + PAD_NC(GPP_H14, NONE), + /* GPP_H15: NC */ + PAD_NC(GPP_H15, NONE), + /* GPP_H16: NC */ + PAD_NC(GPP_H16, NONE), + /* GPP_H17: SOC_HP_INT_L */ + PAD_CFG_GPI(GPP_H17, NONE, DEEP), + /* GPP_H19: I3C0_SDA_HDR */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2), + /* GPP_H20: I3C0_SCL_HDR */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2), + /* GPP_H21: CAL_SDA_IN */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22: CAL_SCL_IN */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S00: I2S_SPK_AUDIO_R_TX */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6), + /* GPP_S01: I2S_SPK_AUDIO_R_RX */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6), + /* GPP_S02: I2S_SPK_BCLK*/ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6), + /* GPP_S03: I2S_SPK_LRCK */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6), + /* GPP_S04: DMIC_CLK_A0 */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* GPP_S05: DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), + /* GPP_S06: NC */ + PAD_NC(GPP_S06, NONE), + /* GPP_S07: NC */ + PAD_NC(GPP_S07, NONE), + + /* GPP_V00: PM_BATLOW_N */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01: BC_ACOK_MCP */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02: LANWAKE_N_R */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03: PWRBTN_MCP_N */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04: PM_SLP_S3_N */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05: PM_SLP_S4_N */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06: PM_SLP_A_N */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07: SUSCLK */ + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), + /* GPP_V08: SLP_WLAN_N */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09: PM_SLP_S5_N */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10: LANPHYPC_R_N */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11: PM_SLP_LAN_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12: WAKE_N */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13: GPP_V13_CATERR_N */ + PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), + /* GPP_V14: GPP_V14_FORCEPR_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15: GPP_V15_THERMTRIP_N */ + PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), + /* GPP_V16: GPP_V16_VCCST_EN */ + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), + /* GPP_V17: SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_V17, 1, PLTRST), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_B14: MOD_TCSS2_DISP_HPD4 */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), + /* GPP_C22: MOD_TCSS2_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: MOD_TCSS2_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + /* GPP_H08: UART0_BUF_RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART0_BUF_TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_E02: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E02, NONE, PLTRST, LEVEL, INVERT), +}; + +/* Pad configuration in romstage */ +static const struct pad_config romstage_gpio_table[] = { + /* GPP_B16: EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + /* GPP_B09: SSD_GEN4_PERST_L */ + PAD_CFG_GPO(GPP_B09, 1, PLTRST), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/fatcat/variants/ruby/hda_verb.c b/src/mainboard/google/fatcat/variants/ruby/hda_verb.c new file mode 100644 index 0000000000..2f703b78ee --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/hda_verb.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */ + 0x10ec12ac, /* Subsystem ID */ + 0x00000013, /* Number of jacks (NID entries) */ + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting-1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h b/src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h new file mode 100644 index 0000000000..4fc0622f15 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h new file mode 100644 index 0000000000..cced66807a --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/ruby/memory.c b/src/mainboard/google/fatcat/variants/ruby/memory.c new file mode 100644 index 0000000000..b8b00f7f51 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/memory.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 14, 12, 15, 11, 10, 8, 9, }, + .dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 }, + }, + .ddr1 = { + .dq0 = { 1, 3, 0, 2, 7, 4, 6, 5, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, + }, + .ddr2 = { + .dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 14, 13, 15, 12, 8, 11, 10, 9, }, + }, + .ddr3 = { + .dq0 = { 6, 5, 7, 4, 2, 3, 1, 0, }, + .dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 }, + }, + .ddr4 = { + .dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 }, + .dq1 = { 15, 14, 12, 13, 9, 11, 10, 8, }, + }, + .ddr5 = { + .dq0 = { 6, 5, 7, 4, 3, 1, 0, 2, }, + .dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 }, + }, + .ddr6 = { + .dq0 = { 9, 10, 11, 8, 14, 12, 13, 15, }, + .dq1 = { 0, 1, 2, 3, 5, 7, 4, 6 }, + }, + .ddr7 = { + .dq0 = { 0, 1, 2, 3, 7, 5, 6, 4, }, + .dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); + +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_A13 + * GPIO_MEM_CONFIG_1 GPP_D24 + * GPIO_MEM_CONFIG_2 GPP_B25 + * GPIO_MEM_CONFIG_3 GPP_B24 + */ + gpio_t spd_gpios[] = { + GPP_A13, + GPP_D24, + GPP_B25, + GPP_B24, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_C07 */ + return gpio_get(GPP_C07); +} diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk new file mode 100644 index 0000000000..e58d787420 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/memory/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /tmp/go-build4042912853/b001/exe/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 0(0b0000) Parts = H58G56CK8BX146 diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt new file mode 100644 index 0000000000..4248666b32 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /tmp/go-build4042912853/b001/exe/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/ruby/memory/ src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H58G56CK8BX146 0 (0000) diff --git a/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt new file mode 100644 index 0000000000..49d566c412 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +H58G56CK8BX146 diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb new file mode 100644 index 0000000000..fe8c7eaadc --- /dev/null +++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb @@ -0,0 +1,302 @@ +chip soc/intel/pantherlake + + # The initial version temporarily uses the PTL-H, + # but the thermal design is based on the PTL-U. + # Apply PTL-U's thermal settings here to avoid thermal issues. + register "power_limits_config[PTL_CORE_1]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 152, + }" + + register "power_limits_config[PTL_CORE_2]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 152, + }" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # no use + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 Type-A (DB) + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1 + + register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + # Enable EDP in PortA + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + }" + + # Enable CNVi Wi-Fi and Bluetooth + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0A] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio ALC5682 | + #| I2C1 | PMIC | + #| I2C2 | ISH_I2C SENSOR | + #| I2C3 | TPM(cr50) | + #| I2C4 | Touchpad | + #| I2C5 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + /* Render OEM footer logo 100px above from the edge */ + .logo_bottom_margin = 100, + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "4" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device generic 0 on end + end + end + + device ref iaa off end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + + end + end + end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 FPMCU"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" + device ref usb2_port7 on end + end + end + end + end + + device ref pcie_rp5 on + register "pcie_rp[PCIE_RP(5)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)" + register "srcclk_pin" = "6" + device generic 0 on end + end + end # Gen4 M.2 SSD + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion + device generic 0 on end + end + end # CNVi + + device ref cnvi_bluetooth on end + + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. + # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H17)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + #probe AUDIO ALC5682I_I2S + end + end + end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E02_IRQ)" + device i2c 50 on end + end + end # I2C3 + device ref i2c4 on + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2305"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)" + # NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb. + register "generic.wake" = "GPE0_DW2_18" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 68 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)" + register "generic.wake" = "GPE0_DW2_18" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C4 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "generic.reset_delay_ms" = "150" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "generic.enable_delay_ms" = "6" + register "generic.enable_off_delay_ms" = "30" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.use_gpio_for_status" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end # I2C5 + device ref gspi0 on end + device ref smbus on end + end +end