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cpu/intel: Refactor platform_enter_postcar()

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There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().

Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-08-09 09:37:49 +03:00
commit 5bc641afeb
14 changed files with 93 additions and 165 deletions
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18
src/cpu/intel/car/romstage.c
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@ -22,6 +22,21 @@
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
static struct postcar_frame early_mtrrs;
/* prepare_and_run_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void prepare_and_run_postcar(struct postcar_frame *pcf)
{
if (postcar_frame_init(pcf, 0))
die("Unable to initialize postcar frame.\n");
fill_postcar_frame(pcf);
run_postcar_phase(pcf);
/* We do not return here. */
}
static void romstage_main(unsigned long bist)
{
int i;
@ -52,7 +67,8 @@ static void romstage_main(unsigned long bist)
printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
}
platform_enter_postcar();
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
}
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)