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soc/intel/common: Include Alder Lake-N device IDs

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Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP),
IGD device IDs.

Document Number: 619501, 645548

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Usha P 2021-11-15 18:40:00 +05:30 • committed by Felix Held
commit 5b94cd9e9d
6 changed files with 20 additions and 0 deletions
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1
src/include/cpu/intel/cpu_ids.h
View file

@ -55,5 +55,6 @@
#define CPUID_ALDERLAKE_A1 0x906a1
#define CPUID_ALDERLAKE_A2 0x906a2
#define CPUID_ALDERLAKE_A3 0x906a4
#define CPUID_ALDERLAKE_N_A0 0xb06e0
#endif /* CPU_INTEL_CPU_IDS_H */

7
src/include/device/pci_ids.h
View file

@ -3886,6 +3886,10 @@
#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
#define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa
#define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3
#define PCI_DEVICE_ID_INTEL_ADL_N_GT1 0x46D0
#define PCI_DEVICE_ID_INTEL_ADL_N_GT2 0x46D1
#define PCI_DEVICE_ID_INTEL_ADL_N_GT3 0x46D2
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@ -3997,6 +4001,9 @@
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f
#define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602
#define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a
#define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617
#define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22
#define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22