diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c index afd8a63084..a0f12c2a8b 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c @@ -248,11 +248,6 @@ static const struct pad_config gen4_ssd_pads[] = { PAD_CFG_GPO(GPP_B09, 1, PLTRST), }; -static const struct pad_config ufs_enable_pads[] = { - /* GPP_D21: GPP_D21_UFS_REFCLK */ - PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -}; - /* Gen5 NVME: at the bottom M.2 slot */ static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = { /* GPP_B16: GEN5_SSD_PWREN */ @@ -601,11 +596,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { - GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); + die("UFS is not supported on Panther Lake\n"); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); - GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); } if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) { diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb index 68136d26ea..6a945727aa 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb @@ -39,7 +39,7 @@ fw_config option STORAGE_UNKNOWN 0 option STORAGE_NVME_GEN4 1 option STORAGE_NVME_GEN5 2 - option STORAGE_UFS 3 + option STORAGE_UFS 3 # Not supported end field FP 17 option FP_ABSENT 0 @@ -518,11 +518,6 @@ chip soc/intel/pantherlake end end - device ref ufs on - probe STORAGE STORAGE_UFS - probe STORAGE STORAGE_UNKNOWN - end - device ref pcie_rp2 on probe CELLULAR CELLULAR_PCIE register "pcie_rp[PCIE_RP(2)]" = "{ diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb index 033a0b475b..52af027cad 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb @@ -39,7 +39,7 @@ fw_config option STORAGE_UNKNOWN 0 option STORAGE_NVME_GEN4 1 option STORAGE_NVME_GEN5 2 - option STORAGE_UFS 3 + option STORAGE_UFS 3 # Not supported end field FP 17 option FP_ABSENT 0 @@ -518,11 +518,6 @@ chip soc/intel/pantherlake end end - device ref ufs on - probe STORAGE STORAGE_UFS - probe STORAGE STORAGE_UNKNOWN - end - device ref pcie_rp2 on probe CELLULAR CELLULAR_PCIE register "pcie_rp[PCIE_RP(2)]" = "{