From 5aebeb4056faf13faf9e384ec87c07fb19f03ae7 Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 4 Feb 2025 15:42:45 +0100 Subject: [PATCH] soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44 Signed-off-by: Maximilian Brune Reviewed-on: https://review.coreboot.org/c/coreboot/+/86270 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/glinda/chipset.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index f328797ec2..a76be1ad31 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -32,7 +32,7 @@ chip soc/amd/glinda device pci 03.6 alias gpp_bridge_3_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) @@ -56,13 +56,13 @@ chip soc/amd/glinda device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable device pci 0.1 alias npu off end # Neural Processing Unit (NPU) end - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_0 off