From 5ae3eb31bda79245f286c78417a9520e2308e92c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 9 Mar 2017 00:42:42 +0200 Subject: [PATCH] UPSTREAM: binaryPI: Fix SSE regression and align stack early When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. For some builds, new toolchain and GCC-6.3 could emit SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. BUG=none BRANCH=none TEST=none Change-Id: I8cf0cd97d9191e23f1f9ce0b8ae647f523a076cd Signed-off-by: Patrick Georgi Original-Commit-Id: bf3091bae688606f9cbd69064bf6deeeddb81d1b Original-Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/18691 Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Nico Huber Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/456301 --- src/cpu/amd/pi/cache_as_ram.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index 24db6001ea..c0a69ec74a 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -63,6 +63,9 @@ cache_as_ram_setup: AMD_ENABLE_STACK + /* Align the stack. */ + and $0xFFFFFFF0, %esp + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -111,8 +114,6 @@ cache_as_ram_setup: /* Pass the BIST result */ cvtsd2si %xmm0, %edi - /* align the stack */ - and $0xFFFFFFF0, %esp .code64 call cache_as_ram_main @@ -126,6 +127,9 @@ cache_as_ram_setup: /* Restore the cpu_init_detected */ cvtsd2si %xmm1, %ebx + /* Must maintain 16-byte stack alignment here. */ + pushl $0x0 + pushl $0x0 pushl %ebx /* init detected */ pushl %edx /* bist */ call cache_as_ram_main