diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index a6e794d08c..1b6b0aecb3 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -210,6 +210,11 @@ enum slew_rate {
 	SLEW_IGNORE = 0xff,
 };
 
+enum tdc_mode {
+	TDC_IPL2,
+	TDC_IRMS,
+};
+
 struct soc_intel_pantherlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -417,6 +422,30 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint16_t thermal_design_current[MAX_PTL_SKUS][NUM_VR_DOMAINS];
 
+	/*
+	 * Thermal Design Current (TDC) mode for each Voltage Regulator (VR) domain.
+	 *
+	 * The mode indicates the method used for managing thermal constraints and power
+	 * consumption based on current measurement techniques.
+	 *
+	 * Possible values:
+	 * - 0: iPL2
+	 * - 1: Irms
+	 */
+	uint8_t tdc_mode[NUM_VR_DOMAINS];
+
+	/*
+	 * Time Window for Thermal Design Current (TDC) for each Voltage Regulator (VR)
+	 * domain.
+	 *
+	 * This array specifies the time window for TDC measurement for each VR
+	 * domain. The TDC time window determines the duration over which the current is
+	 * averaged.
+	 *
+	 * Units are milliseconds.
+	 */
+	uint32_t tdc_time_window_ms[NUM_VR_DOMAINS];
+
 	/*
 	 * Maximum Integrated Current Capability (ICC) settings for various SKUs.
 	 *
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 2498bec4e2..c0dd691836 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -352,6 +352,11 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 			continue;
 		m_cfg->IccMax[i] = config->icc_max[map->sku][i];
 	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->tdc_mode); i++) {
+		m_cfg->TdcMode[i] = config->tdc_mode[i];
+		m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i];
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)