erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver

Browse source 
These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.

Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.

Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier 2018-08-01 13:53:04 -05:00 • committed by Patrick Georgi
commit 59962f3015
16 changed files with 17 additions and 81 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/mainboard/google/auron/variants/auron_paine/devicetree.cb
View file

@ -91,11 +91,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
View file

@ -91,11 +91,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

8
src/mainboard/google/auron/variants/gandof/devicetree.cb
View file

@ -90,12 +90,8 @@ chip soc/intel/broadwell
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/auron/variants/lulu/devicetree.cb
View file

@ -92,11 +92,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/auron/variants/samus/devicetree.cb
View file

@ -95,11 +95,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/banon/devicetree.cb
View file

@ -135,11 +135,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/celes/devicetree.cb
View file

@ -135,11 +135,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/cyan/devicetree.cb
View file

@ -128,11 +128,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/edgar/devicetree.cb
View file

@ -129,11 +129,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/kefka/devicetree.cb
View file

@ -142,11 +142,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/reks/devicetree.cb
View file

@ -126,11 +126,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/relm/devicetree.cb
View file

@ -142,11 +142,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/setzer/devicetree.cb
View file

@ -135,11 +135,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/terra/devicetree.cb
View file

@ -135,11 +135,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/ultima/devicetree.cb
View file

@ -129,11 +129,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end

6
src/mainboard/google/cyan/variants/wizpig/devicetree.cb
View file

@ -136,11 +136,7 @@ chip soc/intel/braswell
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end