From 590f6b9b79f256ff17225dfc446e7afb27797c16 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Tue, 1 Apr 2025 17:53:40 +0530 Subject: [PATCH] mb/google/brya/var/gimble: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on gimble device and verify that the device suspends to S0ix. Change-Id: Iac9eb63639cbb0c7708d5b2bb30aca20e09db3e7 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/87061 Tested-by: build bot (Jenkins) Reviewed-by: Jayvik Desai Reviewed-by: Kapil Porwal --- .../google/brya/variants/gimble/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 4f1bcdcfb9..762c3ffa4a 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -159,6 +159,15 @@ chip soc/intel/alderlake device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end #PCIE9-12 SSD device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682""