From 58f162b07e0689cf516633e5496da0f5e880b122 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Tue, 11 Mar 2025 15:06:18 +0800 Subject: [PATCH] mb/google/nissa/var/yavilla: Update eMMC DLL settings Update eMMC DLL settings to prevent Ramaxel eMMC initialization error. BUG=b:402260689 TEST=Verify on Ramaxel emmc warm/cold reboot stress test pass Verify on current emmc warm/cold reboot stress test pass Change-Id: I2c560d63de7b596ee05ceb95726e4cb8001cf730 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/86812 Reviewed-by: Wisley Chen Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/yavilla/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index be926179dc..015228e2c1 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -76,7 +76,7 @@ chip soc/intel/alderlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C171733" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C17171B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12.