From 58ee4a7f634711ee091841bd6669022a24e60f43 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Sat, 14 Dec 2013 10:31:54 +0800 Subject: [PATCH] tegra124: Fix bloated ROM stage. The ROMSTAGE_BASE currently must be aligned to 0x8000 bytes, otherwise linker will try to do that and pad zeros, creating a large (ex, >40k) romstage blob, which cannot be loaded properly. BUG=none TEST=Boots successfully on Nyan. Change-Id: I7626542c8344bbf6641a200879e4aa18183dc1bd Reviewed-on: https://chromium-review.googlesource.com/180150 Reviewed-by: David Hendricks Reviewed-by: Hung-Te Lin Commit-Queue: Hung-Te Lin Tested-by: Hung-Te Lin --- src/soc/nvidia/tegra124/Kconfig | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 23f48f2c0d..89e9ae2d78 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -37,8 +37,8 @@ config BOOTBLOCK_CPU_INIT # +4000 (Coreboot) Stack. # 0x4000_E000 Valid for anything to be executed after BootROM (effective entry # point address specified in BCT). -# +0000 (Coreboot) Bootblock (max 36k). -# +9000 (Coreboot) ROM stage (max 36k). +# +0000 (Coreboot) Bootblock (max 40k). +# +A000 (Coreboot) ROM stage (max 32k). # 0x4002_0000 (Coreboot) Cache of CBFS. # 0x4003_FFFF End of iRAM. @@ -62,9 +62,10 @@ config BOOTBLOCK_BASE hex default 0x4000e000 +# Note ROMSTAGE_BASE must be aligned to 0x8000. config ROMSTAGE_BASE hex - default 0x40017000 + default 0x40018000 config RAMSTAGE_BASE hex