diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig new file mode 100644 index 0000000000..728f81e7c1 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/Kconfig @@ -0,0 +1,48 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_QUALCOMM_X1P42100 + bool + default n + depends on USE_QC_BLOBS + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select CACHE_MRC_SETTINGS + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_SD + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAS_RECOVERY_MRC_CACHE + select HAVE_LINEAR_FRAMEBUFFER + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select SDHCI_CONTROLLER + select SOC_QUALCOMM_COMMON + +if SOC_QUALCOMM_X1P42100 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/x1p42100/memlayout.ld" + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 0 # TODO + +config UART_FOR_CONSOLE + int + default 0 # TODO + help + Select the QUP instance to be used for UART console output. + +endif diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk new file mode 100644 index 0000000000..0135f9bf57 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/Makefile.mk @@ -0,0 +1,162 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_QUALCOMM_X1P42100),y) + +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += ../common/timer.c +all-y += ../common/timer.c +all-y += ../common/gpio.c +all-y += clock.c +all-y += ../common/spi.c +all-y += ../common/qspi.c +all-y += ../common/qupv3_config.c +all-y += qcom_qup_se.c +all-y += ../common/qup_se_handler.c +all-y += ../common/qupv3_spi.c +all-y += ../common/qupv3_i2c.c +all-y += ../common/qupv3_spi.c + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c + +################################################################################ +verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += shrm_load_reset.c +romstage-y += cpucp_load_reset.c +romstage-y += ../common/qclib.c +romstage-y += ../common/mmu.c +romstage-y += ../common/watchdog.c +romstage-y += mmu.c +romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-y += cpucp_load_reset.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/x1p42100/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ +ifeq ($(CONFIG_USE_QC_BLOBS),y) +# TODO: Upload X1P42100 SoC blobs +X1P42100_BLOB := $(top)/3rdparty/qc_blobs/sc7280 + +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +BL31_MAKEARGS += QTI_SDI_BUILD=1 +BL31_MAKEARGS += QTISECLIB_PATH=$(X1P42100_BLOB)/qtiseclib/libqtisec_dbg.a +else +BL31_MAKEARGS += QTISECLIB_PATH=$(X1P42100_BLOB)/qtiseclib/libqtisec.a +endif # CONFIG_QC_SDI_ENABLE + +################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(X1P42100_BLOB)/boot/QcSdi.elf +QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi +$(QCSDI_CBFS)-file := $(QCSDI_FILE) +$(QCSDI_CBFS)-type := stage +$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(QCSDI_CBFS) +endif + +################################################################################ +QC_SEC_FILE := $(X1P42100_BLOB)/qc_sec/qc_sec.mbn +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin + +################################################################################ +QCLIB_FILE := $(X1P42100_BLOB)/boot/QcLib.elf +QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib +$(QCLIB_CBFS)-file := $(QCLIB_FILE) +$(QCLIB_CBFS)-type := stage +$(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(QCLIB_CBFS) + +################################################################################ +PMIC_FILE := $(X1P42100_BLOB)/boot/Pmic.bin +PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg +$(PMIC_CBFS)-file := $(PMIC_FILE) +$(PMIC_CBFS)-type := raw +$(PMIC_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(PMIC_CBFS) + +################################################################################ +DCB_FILE := $(X1P42100_BLOB)/boot/dcb.bin +DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb +$(DCB_CBFS)-file := $(DCB_FILE) +$(DCB_CBFS)-type := raw +$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DCB_CBFS) + +################################################################################ +UART_FW_FILE := $(X1P42100_BLOB)/qup_fw/uart_fw.bin +UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw +$(UART_FW_CBFS)-file := $(UART_FW_FILE) +$(UART_FW_CBFS)-type := raw +$(UART_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(UART_FW_CBFS) + +################################################################################ +SPI_FW_FILE := $(X1P42100_BLOB)/qup_fw/spi_fw.bin +SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw +$(SPI_FW_CBFS)-file := $(SPI_FW_FILE) +$(SPI_FW_CBFS)-type := raw +$(SPI_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(SPI_FW_CBFS) + +################################################################################ +I2C_FW_FILE := $(X1P42100_BLOB)/qup_fw/i2c_fw.bin +I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw +$(I2C_FW_CBFS)-file := $(I2C_FW_FILE) +$(I2C_FW_CBFS)-type := raw +$(I2C_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(I2C_FW_CBFS) + +################################################################################ +AOP_FILE := $(X1P42100_BLOB)/aop/aop.mbn +AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop +$(AOP_CBFS)-file := $(AOP_FILE) +$(AOP_CBFS)-type := payload +$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_CBFS) + +################################################################################ +CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf +CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp +$(CPUCP_CBFS)-file := $(CPUCP_FILE) +$(CPUCP_CBFS)-type := payload +$(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(CPUCP_CBFS) + +################################################################################ +SHRM_FILE := $(X1P42100_BLOB)/shrm/shrm.elf +SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm +$(SHRM_CBFS)-file := $(SHRM_FILE) +$(SHRM_CBFS)-type := payload +$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(SHRM_CBFS) + +################################################################################ +GSI_FW_FILE := $(X1P42100_BLOB)/qup_fw/gsi_fw.bin +GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw +$(GSI_FW_CBFS)-file := $(GSI_FW_FILE) +$(GSI_FW_CBFS)-type := raw +$(GSI_FW_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(GSI_FW_CBFS) + +endif + +endif diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c new file mode 100644 index 0000000000..a4cedfa69f --- /dev/null +++ b/src/soc/qualcomm/x1p42100/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_soc_init(void) +{ + if (!CONFIG(COMPRESS_BOOTBLOCK)) + soc_mmu_init(); +} diff --git a/src/soc/qualcomm/x1p42100/cbmem.c b/src/soc/qualcomm/x1p42100/cbmem.c new file mode 100644 index 0000000000..5fff371d58 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/cbmem.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)4 * GiB; +} diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c new file mode 100644 index 0000000000..9a4b16d810 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/clock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void clock_configure_qspi(uint32_t hz) +{ + /* placeholder */ +} + +void clock_enable_qup(int qup) +{ + /* placeholder */ +} + +void clock_configure_dfsr(int qup) +{ + /* placeholder */ +} diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c new file mode 100644 index 0000000000..f415bb8555 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void cpucp_prepare(void) +{ + /* Placeholder */ +} + +void cpucp_fw_load_reset(void) +{ + /* Placeholder */ +} diff --git a/src/soc/qualcomm/x1p42100/decompressor.c b/src/soc/qualcomm/x1p42100/decompressor.c new file mode 100644 index 0000000000..12a3bac50b --- /dev/null +++ b/src/soc/qualcomm/x1p42100/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void decompressor_soc_init(void) +{ + soc_mmu_init(); +} diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h new file mode 100644 index 0000000000..5bb39e3bb5 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H_ + +#include + +/* TODO: update as per datasheet */ +#define AOSS_CC_BASE 0x0C2A0000 +#define QSPI_BASE 0x088DC000 +#define TLMM_TILE_BASE 0x0F100000 + +/* X1P42100 QSPI GPIO PINS */ +#define QSPI_CS GPIO(0) +#define QSPI_DATA_0 GPIO(0) +#define QSPI_DATA_1 GPIO(0) +#define QSPI_CLK GPIO(0) + +#define GPIO_FUNC_QSPI_DATA_0 0 +#define GPIO_FUNC_QSPI_DATA_1 0 +#define GPIO_FUNC_QSPI_CLK 0 + +/* + * QUP SERIAL ENGINE BASE ADDRESSES + */ +/* QUPV3_0 */ +#define QUP_SERIAL0_BASE 0x00980000 +#define QUP_SERIAL1_BASE 0x00984000 +#define QUP_SERIAL2_BASE 0x00988000 +#define QUP_SERIAL3_BASE 0x0098C000 +#define QUP_SERIAL4_BASE 0x00990000 +#define QUP_SERIAL5_BASE 0x00994000 +#define QUP_SERIAL6_BASE 0x00998000 +#define QUP_SERIAL7_BASE 0x0099C000 +#define QUP_WRAP0_BASE 0x009C0000 +#define QUP_0_GSI_BASE 0x00904000 + +/* QUPV3_1 */ +#define QUP_SERIAL8_BASE 0x00A80000 +#define QUP_SERIAL9_BASE 0x00A84000 +#define QUP_SERIAL10_BASE 0x00A88000 +#define QUP_SERIAL11_BASE 0x00A8C000 +#define QUP_SERIAL12_BASE 0x00A90000 +#define QUP_SERIAL13_BASE 0x00A94000 +#define QUP_SERIAL14_BASE 0x00A98000 +#define QUP_SERIAL15_BASE 0x00A9C000 +#define QUP_WRAP1_BASE 0x00AC0000 +#define QUP_1_GSI_BASE 0x00A04000 + +/* QUPV3_2 - Dummy Entry */ +#define QUP_WRAP2_BASE 0x00000000 + +#endif /* __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h new file mode 100644 index 0000000000..97d418fdbb --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#ifndef __SOC_QUALCOMM_X1P42100_CLOCK_H__ +#define __SOC_QUALCOMM_X1P42100_CLOCK_H__ + +#define SRC_XO_HZ (38400 * KHz) + +/* TODO: update as per datasheet */ +void clock_configure_qspi(uint32_t hz); +void clock_enable_qup(int qup); +void clock_configure_dfsr(int qup); + +/* Subsystem Reset */ +static struct aoss *const aoss = (void *)AOSS_CC_BASE; + +#endif // __SOC_QUALCOMM_X1P42100_CLOCK_H__ diff --git a/src/soc/qualcomm/x1p42100/include/soc/cpucp.h b/src/soc/qualcomm/x1p42100/include/soc/cpucp.h new file mode 100644 index 0000000000..4aa7384da7 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/cpucp.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_CPUCP_H__ +#define _SOC_QUALCOMM_X1P42100_CPUCP_H__ + +void cpucp_fw_load_reset(void); +void cpucp_prepare(void); + +#endif // _SOC_QUALCOMM_X1P42100_CPUCP_H__ diff --git a/src/soc/qualcomm/x1p42100/include/soc/gpio.h b/src/soc/qualcomm/x1p42100/include/soc/gpio.h new file mode 100644 index 0000000000..1c30f7881f --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_GPIO_H_ +#define _SOC_QUALCOMM_X1P42100_GPIO_H_ + +#include +#include +#include + +#define PIN(index, func1, func2, func3, func4) \ +GPIO##index##_ADDR = TLMM_TILE_BASE + (index * TLMM_GPIO_OFF_DELTA), \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4 + +/* TODO: update as per datasheet */ +enum { + PIN(0, QUP0_L0, RES_2, RES_3, RES_4), +}; + +#endif /* _SOC_QUALCOMM_X1P42100_GPIO_H_ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/mmu.h b/src/soc/qualcomm/x1p42100/include/soc/mmu.h new file mode 100644 index 0000000000..a0a25ba05b --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_MMU_H_ +#define _SOC_QUALCOMM_X1P42100_MMU_H_ + +void soc_mmu_init(void); + +#endif /* _SOC_QUALCOMM_X1P42100_MMU_H_ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h new file mode 100644 index 0000000000..f12616a51f --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QCOM_QUP_SE_H__ +#define __SOC_QCOM_QUP_SE_H__ + +#include +#include +#include +#include +#include +#include + +/* TODO: update qup_se entries as per datasheet */ +enum qup_se { + QUPV3_0_SE0, + QUPV3_0_SE1, + QUPV3_0_SE2, + QUPV3_0_SE3, + QUPV3_0_SE4, + QUPV3_0_SE5, + QUPV3_0_SE6, + QUPV3_0_SE7, + QUPV3_0_SE8, + QUPV3_SE_MAX, +}; + +struct qup { + struct qup_regs *regs; + gpio_t pin[4]; + u8 func[4]; +}; + +extern struct qup qup[QUPV3_SE_MAX]; + +/* TODO: update MAX_OFFSET_CFG_REG as per datasheet */ +#define MAX_OFFSET_CFG_REG 0x000001c4 + +#endif /* __SOC_QCOM_QUP_SE_H__ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/sdhci.h b/src/soc/qualcomm/x1p42100/include/soc/sdhci.h new file mode 100644 index 0000000000..3e5f10793a --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/sdhci.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_SDHCI_H__ +#define _SOC_QUALCOMM_X1P42100_SDHCI_H__ + +int qc_emmc_early_init(void); + +#endif // _SOC_QUALCOMM_X1P42100_SDHCI_H__ diff --git a/src/soc/qualcomm/x1p42100/include/soc/shrm.h b/src/soc/qualcomm/x1p42100/include/soc/shrm.h new file mode 100644 index 0000000000..667e257e6c --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/shrm.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_SHRM_H__ +#define _SOC_QUALCOMM_X1P42100_SHRM_H__ + +void shrm_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_X1P42100_SHRM_H__ diff --git a/src/soc/qualcomm/x1p42100/include/soc/uart.h b/src/soc/qualcomm/x1p42100/include/soc/uart.h new file mode 100644 index 0000000000..179deb3021 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/uart.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_X1P42100_UART_TX_H_ +#define _SOC_QUALCOMM_X1P42100_UART_TX_H_ + +#define UART_TX_PIN GPIO(0) + +#endif /* _SOC_QUALCOMM_X1P42100_UART_TX_H_ */ diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld new file mode 100644 index 0000000000..c2e2f90766 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/memlayout.ld @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Copied from Qualcomm previous generation SoC SC7280 and need cleanup */ + +/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */ +#define SSRAM_START(addr) REGION_START(ssram, addr) +#define SSRAM_END(addr) REGION_END(ssram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) REGION_START(bsram, addr) +#define BSRAM_END(addr) REGION_END(bsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) REGION_START(aopsram, addr) +#define AOPSRAM_END(addr) REGION_END(aopsram, addr) + +SECTIONS +{ + REGION(shrm, 0x09060000, 64K , 4K) + + AOPSRAM_START(0x0B000000) + REGION(aop_code_ram, 0x0B000000, 0x80000, 4096) + REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096) + AOPSRAM_END(0x0B100000) + + SSRAM_START(0x14680000) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 132K) + REGION(qcsdi, 0x146A1000, 40K, 4K) + SSRAM_END(0x146AB000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + WATCHDOG_TOMBSTONE(0x14818FFC, 4) + BOOTBLOCK(0x14819000, 60K) + PRERAM_CBFS_CACHE(0x14828000, 103K) + TIMESTAMP(0x14841C00, 1K) + TTB(0x14842000, 56K) + STACK(0x14850000, 16K) + VBOOT2_WORK(0x14854000, 12K) + DMA_COHERENT(0x14857000, 8K) + REGION(qclib_serial_log, 0x1485B000, 4K, 4K) + CBFS_MCACHE(0x1485C000,16K) + REGION(ddr_information, 0x14860000, 1K, 1K) + FMAP_CACHE(0x14860400, 2K) + REGION(dcb, 0x14862000, 32K, 4K) + REGION(pmic, 0x1486A000, 96K, 4K) + REGION(ddr_training, 0x14882000, 32K, 4K) + REGION(qclib, 0x1488A000, 800K, 4K) + PRERAM_CBMEM_CONSOLE(0x14954000, 32K) + BSRAM_END(0x1495C000) + + DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) + BL31(0xC0000000, 1M) +} diff --git a/src/soc/qualcomm/x1p42100/mmu.c b/src/soc/qualcomm/x1p42100/mmu.c new file mode 100644 index 0000000000..9279d8e1a0 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/mmu.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void soc_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/x1p42100/pcie.c b/src/soc/qualcomm/x1p42100/pcie.c new file mode 100644 index 0000000000..3e38450c4b --- /dev/null +++ b/src/soc/qualcomm/x1p42100/pcie.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Enable PIPE clock */ +int qcom_dw_pcie_enable_pipe_clock(void) +{ + /* placeholder */ + + return 0; +} + +/* Enable controller specific clocks */ +int32_t qcom_dw_pcie_enable_clock(void) +{ + /* placeholder */ + + return 0; +} + +/* Turn on NVMe */ +void gcom_pcie_power_on_ep(void) +{ + /* placeholder */ +} + +void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg) +{ + /* placeholder */ +} diff --git a/src/soc/qualcomm/x1p42100/qcom_qup_se.c b/src/soc/qualcomm/x1p42100/qcom_qup_se.c new file mode 100644 index 0000000000..8b2284d4b1 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/qcom_qup_se.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* TODO: update qup entries as per datasheet */ +struct qup qup[QUPV3_SE_MAX] = { + +}; diff --git a/src/soc/qualcomm/x1p42100/shrm_load_reset.c b/src/soc/qualcomm/x1p42100/shrm_load_reset.c new file mode 100644 index 0000000000..6bd1b1d530 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/shrm_load_reset.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void shrm_fw_load_reset(void) +{ + /* Placeholder */ +} diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c new file mode 100644 index 0000000000..c23aa89c69 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/soc.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +static struct device_operations pci_domain_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + +static void soc_read_resources(struct device *dev) +{ + /* placeholder */ +} + +static void soc_init(struct device *dev) +{ + /* placeholder */ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .set_resources = noop_set_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + if (mainboard_needs_pcie_init()) + dev->ops = &pci_domain_ops; + else + printk(BIOS_DEBUG, "Skip setting PCIe ops\n"); + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_x1p42100_ops = { + .name = "SOC Qualcomm X1P-42-100", + .enable_dev = enable_soc_dev, +};