From 57ae756c2684e1612bf26083588365677730b453 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 7 May 2001 01:42:59 +0000 Subject: [PATCH] manpreet's new files for 440bx. The name 'l440gx' is sort of a generic mainboard. --- src/mainboard/intel/l440bx/BUILD_PHLASH_FILES | 16 ++ src/mainboard/intel/l440bx/Config | 56 +++++ src/mainboard/intel/l440bx/Makefile | 94 ++++++++ src/mainboard/intel/l440bx/crt0.S | 121 ++++++++++ src/mainboard/intel/l440bx/ldscript.ld | 116 ++++++++++ src/mainboard/intel/l440bx/mainboard.c | 181 +++++++++++++++ src/superio/SMC/fdc37c669/setup_serial.inc | 96 ++++++++ src/superio/SMC/fdc37c669/superio.c | 215 ++++++++++++++++++ src/superio/SMC/fdc37c669/superio.h | 17 ++ util/config/l440bx-test12.config | 34 +++ 10 files changed, 946 insertions(+) create mode 100644 src/mainboard/intel/l440bx/BUILD_PHLASH_FILES create mode 100644 src/mainboard/intel/l440bx/Config create mode 100644 src/mainboard/intel/l440bx/Makefile create mode 100644 src/mainboard/intel/l440bx/crt0.S create mode 100644 src/mainboard/intel/l440bx/ldscript.ld create mode 100644 src/mainboard/intel/l440bx/mainboard.c create mode 100644 src/superio/SMC/fdc37c669/setup_serial.inc create mode 100644 src/superio/SMC/fdc37c669/superio.c create mode 100644 src/superio/SMC/fdc37c669/superio.h create mode 100644 util/config/l440bx-test12.config diff --git a/src/mainboard/intel/l440bx/BUILD_PHLASH_FILES b/src/mainboard/intel/l440bx/BUILD_PHLASH_FILES new file mode 100644 index 0000000000..c35df322bb --- /dev/null +++ b/src/mainboard/intel/l440bx/BUILD_PHLASH_FILES @@ -0,0 +1,16 @@ +#!/bin/sh +phlash=$1 +if [ "$phlash" = "" ] ; then + phlash=p11-0102 +fi +dd bs=65696 conv=sync of=/tmp/$phlash.bi1 if=$phlash.bi1 +dd bs=65696 conv=sync of=/tmp/$phlash.bio if=$phlash.bio +dd bs=65696 conv=sync of=/tmp/$phlash.bi3 if=$phlash.bi3 +dd bs=65696 conv=sync of=/tmp/$phlash.bi2 if=$phlash.bi2 +dd bs=65696 conv=sync of=/tmp/$phlash.bi5 if=$phlash.bi5 +dd bs=65696 conv=sync of=/tmp/$phlash.bi4 if=$phlash.bi4 +dd bs=65696 conv=sync of=/tmp/$phlash.bi7 if=$phlash.bi7 +dd bs=65696 conv=sync of=/tmp/$phlash.bi6 if=$phlash.bi6 +dd bs=65696 conv=sync of=/tmp/$phlash.bi9 if=$phlash.bi9 +dd bs=65696 conv=sync of=/tmp/$phlash.bi8 if=$phlash.bi8 +dd bs=65696 conv=sync of=/tmp/$phlash.bia if=$phlash.bia diff --git a/src/mainboard/intel/l440bx/Config b/src/mainboard/intel/l440bx/Config new file mode 100644 index 0000000000..d6e5921281 --- /dev/null +++ b/src/mainboard/intel/l440bx/Config @@ -0,0 +1,56 @@ +northbridge intel/440bx +southbridge intel/piix4e + +superio SMC/fdc37c669 + +option ENABLE_FIXED_AND_VARIABLE_MTRRS +option PIIX4_DEVFN=0x38 +option NO_KEYBOARD +option ZKERNEL_START=0xfffc0000 +option ZKERNEL_MASK=0x7f +option L440BX +option SMC_BASE=0x3F0 + +object mainboard.o + +cpu p6 +cpu p5 + +makerule phlash_floppy: phlash ; mcopy -o /tmp/$(PHLASH_BASE_NAME).bi? a: + +makerule phlash: $(BOOT_IMAGE) linuxbios.rom headers ; rm -f xa? +addaction phlash split -b 64k $(BOOT_IMAGE) +addaction phlash # Now just touch them if we have a really +addaction phlash # small kernel! +addaction phlash touch xaa xab xac xad xae xaf xag xah +addaction phlash # this is starting at bank 4, and proceeding on. Unused banks are dups +addaction phlash # the nvram is odd, all of the banks are interleaved +addaction phlash cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1 #4 +addaction phlash cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3 #6 +addaction phlash cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2 #7 +addaction phlash cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4 #9 +addaction phlash cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7 #a +addaction phlash cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6 #b +addaction phlash cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9 #c +addaction phlash cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8 #d +addaction phlash cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia +addaction phlash # Part o & 5 seem not to be written reliably for some reason... +addaction phlash cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio +addaction phlash cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5 +addaction phlash sh -x $(TOP)/src/mainboard/intel/l440bx/BUILD_PHLASH_FILES $(PHLASH_BASE_NAME) + +makerule headers : $(PHLASH_BASE_NAME).bi1.header $(PHLASH_BASE_NAME).bi2.header $(PHLASH_BASE_NAME).bi3.header $(PHLASH_BASE_NAME).bi4.header $(PHLASH_BASE_NAME).bi5.header $(PHLASH_BASE_NAME).bi6.header $(PHLASH_BASE_NAME).bi7.header $(PHLASH_BASE_NAME).bi8.header $(PHLASH_BASE_NAME).bi9.header $(PHLASH_BASE_NAME).bia.header $(PHLASH_BASE_NAME).bio.header ; + +makerule $(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio ; dd if=$< of=$@ bs=1 count=160 + +addaction clean rm -f $(PHLASH_BASE_NAME)* xa? diff --git a/src/mainboard/intel/l440bx/Makefile b/src/mainboard/intel/l440bx/Makefile new file mode 100644 index 0000000000..66f205c38f --- /dev/null +++ b/src/mainboard/intel/l440bx/Makefile @@ -0,0 +1,94 @@ +CPUFLAGS=-DL440BX -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM +CPUFLAGS += -D__KERNEL__ +CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD +CPUFLAGS += -DSMP +#CPUFLAGS += -DHAVE_FRAMEBUFFER +CPUFLAGS += -DNEWPCI +CPUFLAGS += -DZKERNEL_START=0xfff40000 +CPUFLAGS += -DZKERNEL_MASK=0x3ed +CPUFLAGS += -DSERIAL_CONSOLE +CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"' +CPUFLAGS += -DPIIX4_DEVFN=0x90 +#CPUFLAGS += -DUPDATE_MICROCODE + +phlash_floppy: phlash + mcopy -o /tmp/$(PHLASH_BASE_NAME).bi? a: + +crt0.s: crt0.S ../../chip/intel/intel_start32.S ../../chip/intel/intel_440ram-2.S + +include ../Makefile.common + +# here begins stupid stuff for the phlash program. It's ugly. + +#PHLASH_BASE_NAME=p11-0105 +PHLASH_BASE_NAME=p11-0102 +#PHLASH_BASE_NAME=p12-0115 +#PHLASH_BASE_NAME=p13-0125 + +phlash: vmlinux.bin.gz linuxbios.rom headers + rm -f xa? + split -b 64k vmlinux.bin.gz +# Now just touch them if we have a really +# small kernel! + touch xaa xab xac xad xae xaf xag xah +# this if starting at bank 4, and proceeding on. Unused banks are dups +# intel nvram is odd all of the banks are byte swapped + cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1 + cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3 + cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2 + cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4 + cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7 + cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6 + cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9 + cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8 + cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia + # Part o & 5 seem not to be written reliably for some reason... + cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio + cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5 + sh -x BUILD_PHLASH_FILES $(PHLASH_BASE_NAME) + +headers: \ + $(PHLASH_BASE_NAME).bi1.header \ + $(PHLASH_BASE_NAME).bi2.header \ + $(PHLASH_BASE_NAME).bi3.header \ + $(PHLASH_BASE_NAME).bi4.header \ + $(PHLASH_BASE_NAME).bi5.header \ + $(PHLASH_BASE_NAME).bi6.header \ + $(PHLASH_BASE_NAME).bi7.header \ + $(PHLASH_BASE_NAME).bi8.header \ + $(PHLASH_BASE_NAME).bi9.header \ + $(PHLASH_BASE_NAME).bia.header \ + $(PHLASH_BASE_NAME).bio.header + +# This builds the headers from the intel flash disk. +# we are not distributing this disk; you need to get it. +BUILDHEADER=dd if=$< of=$@ bs=1 count=160 + +$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio + $(BUILDHEADER) + + + +clean:: + rm -f $(PHLASH_BASE_NAME)* + diff --git a/src/mainboard/intel/l440bx/crt0.S b/src/mainboard/intel/l440bx/crt0.S new file mode 100644 index 0000000000..19c0c125e4 --- /dev/null +++ b/src/mainboard/intel/l440bx/crt0.S @@ -0,0 +1,121 @@ +/* + * $ $ + * + */ + +#include +#include + +#include +/* + * This is the entry code (the mkrom(8) utility makes a jumpvector + * to this adddess. + * + * When we get here we are in x86 real mode. + * + * %cs = 0xf000 %ip = 0x0000 + * %ds = 0x0000 %es = 0x0000 + * %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6, + * where x is undefined) + * %fl = 0x0002 + */ + .text + .code16 + +#include + +#include + +#include + +#include + + TTYS0_TX_STRING($ttyS0_test) + + /* initialize the RAM */ + /* different for each motherboard */ + +#include +#include + +#undef RAMTEST +#ifdef RAMTEST +#include + +#include + movl $0x00000000, %eax + movl $0x0009ffff, %ebx + movl $24,%ecx + CALLSP(ramtest) +#if 0 + movl $0x08000000, %eax + movl $0x08001000, %ebx + movl $24,%ecx + CALLSP(ramtest) + + movl $0x10000000, %eax + movl $0x10001000, %ebx + movl $24,%ecx + CALLSP(ramtest) +#endif +#endif + +/* + * Copy data into RAM and clear the BSS. Since these segments + * isn't really that big we just copy/clear using bytes, not + * double words. + */ + intel_chip_post_macro(0x11) /* post 11 */ + TTYS0_TX_STRING($str_after_ram) + + cld /* clear direction flag */ + leal EXT(_ldata), %esi + leal EXT(_data), %edi + movl $EXT(_eldata), %ecx + subl %esi, %ecx + jz .Lnodata /* should not happen */ + rep + movsb +.Lnodata: + intel_chip_post_macro(0x12) /* post 12 */ + TTYS0_TX_STRING($str_after_copy) + + /** clear stack */ + xorl %edi, %edi + movl $_PDATABASE, %ecx + xorl %eax, %eax + rep + stosb + /** clear bss */ + leal EXT(_bss), %edi + movl $EXT(_ebss), %ecx + subl %edi, %ecx + jz .Lnobss + xorl %eax, %eax + rep + stosb +.Lnobss: + +/* + * Now we are finished. Memory is up, data is copied and + * bss is cleared. Now we call the ``main´´ routine and + * let it do the rest. + */ + intel_chip_post_macro(0xfe) /* post fe */ + TTYS0_TX_STRING($str_pre_main) + + /* set new stack */ + movl $_PDATABASE, %esp + + +/* memory is up. Let's do the rest in C -- much easier. */ + call EXT(intel_main) + /*NOTREACHED*/ +.Lhlt: hlt + jmp .Lhlt + +ttyS0_test: .string "\r\n\r\nHello world!!! I am here\r\n" +str_after_ram: .string "Ram Initialize?\r\n" +str_after_copy: .string "after copy?\r\n" +str_pre_main: .string "before main\r\n" +newline: .string "\r\n" diff --git a/src/mainboard/intel/l440bx/ldscript.ld b/src/mainboard/intel/l440bx/ldscript.ld new file mode 100644 index 0000000000..c1669e1d79 --- /dev/null +++ b/src/mainboard/intel/l440bx/ldscript.ld @@ -0,0 +1,116 @@ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * + * $Id$ + * + */ +/* oh, barf. This won't work if all you use is .o's. -- RGM */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* + * Memory map: + * + * 0x00000 (4*4096 bytes) : stack + * 0x04000 (4096 bytes) : private data + * 0x05000 : data space + * 0x90000 : kernel stack + * 0xf0000 (64 Kbyte) : EPROM + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is + * max for STPC */ + rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */ +} + +_PDATABASE = 0x04000; +_RAMBASE = 0x05000; +_KERNSTK = 0x90000; +/* should be parameterized but is not, yuck! */ +/* +_ROMBASE = 0xe0000; + */ +_ROMBASE = 0xf0000; + +/* + * Entry point is not really nececary, since the mkrom(8) + * tool creates a entry point that jumps to $0xc000:0x0000. + */ +/* baloney, but ... RGM*/ +ENTRY(_start) + +SECTIONS { + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text _ROMBASE : { + _text = .; + *(.text); + *(.rodata); + _etext = .; + } + + _pdata = .; + +/* + .pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) + + SIZEOF(.rodata)) { + */ + .pdata _PDATABASE : AT ( _etext ) { + *(.pdata); + } + + _epdata = LOADADDR(.pdata) + SIZEOF(.pdata); + + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) { + _data = .; + *(.data) + *(.sdata) + *(.sdata2) + *(.got) + _edata = .; + } + + _ldata = LOADADDR(.data); + _eldata = LOADADDR(.data) + SIZEOF(.data); + + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between __bss_start and __bss_end with zeroes. + */ + .bss ( ADDR(.data) + SIZEOF(.data) ) : { + _bss = .; + *(.bss) + *(.sbss) + *(COMMON) + _ebss = .; + _heap = .; + } +} + +/* + * This provides the start and end address for the whole image + */ +_image = LOADADDR(.text); +_eimage = LOADADDR(.data) + SIZEOF(.data); + +/* EOF */ diff --git a/src/mainboard/intel/l440bx/mainboard.c b/src/mainboard/intel/l440bx/mainboard.c new file mode 100644 index 0000000000..3d5d8c98c4 --- /dev/null +++ b/src/mainboard/intel/l440bx/mainboard.c @@ -0,0 +1,181 @@ +#include +#include + +#include + +// this needs to be moved about a bit to northbridge.c etc. + + +void mainboard_fixup() +{ + struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev; + unsigned smbus_io, pm_io; + unsigned int i, j; + printk("intel_mainboard_fixup()\n"); + +#if 1 + pm_pcidev = pci_find_device(0x8086, 0x7113, 0); + nic_pcidev = pci_find_device(0x8086, 0x1229, 0); + host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0)); +#endif +#if 1 + pci_write_config_byte(nic_pcidev, 0x3c, 21); +#endif +#if 1 + { + u8 byte; + u16 word; + u32 dword; + for(i = 0; i < 8; i++) { + pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte); + printk("DRB[i] = 0x%02x\n", byte); + } + pci_read_config_byte(host_bridge_pcidev, 0x57, &byte); + printk("DRAMC = 0x%02x\n", byte); + pci_read_config_byte(host_bridge_pcidev, 0x74, &byte); + printk("RPS = 0x%02x\n", byte); + pci_read_config_word(host_bridge_pcidev, 0x78, &word); + printk("PGPOL = 0x%04x\n", word); + pci_read_config_dword(host_bridge_pcidev, 0x50, &dword); + printk("NBXCFG = 0x%04x\n", dword); + } + +#endif +#if 1 + + printk("Reset Control Register\n"); + outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9); + + printk("port 92\n"); + outb((inb(0x92) & 0xFE), 0x92); + + printk("Disable Nmi\n"); + outb(0, 0x70); + + printk("enabling smbus\n"); +#if 0 + smbus_io = NewPciIo(0x10); +#else + smbus_io = 0xFFF0; +#endif + pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */ + pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */ + + + printk("enable pm functions\n"); +#if 0 + pm_io = NewPciIo(0x40); +#else + pm_io = 0xFF80; +#endif + pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */ + + printk("disabling smi\n"); + /* GLBEN */ + outw(0x00, pm_io + 0x20); + /* GLBCTL */ + outl((1 << 24), pm_io + 0x28); + + printk("Disable more pm stuff\n"); + /* PMEN */ + outw((1 << 8), pm_io + 0x02); + /* PMCNTRL */ + outw((0x5 << 10) , pm_io + 0x4); + /* PMTMR */ + outl(0, pm_io + 0x08); + /* GPEN */ + outw(0, pm_io + 0x0e); + /* PCNTRL */ + outl(0, pm_io + 0x10); + /* GLBSTS */ + /* DEVSTS */ + /* GLBEN see above */ + /* GLBCTL see above */ + /* DEVCTL */ + outl(0, pm_io + 0x2c); + /* GPIREG */ + /* GPOREG */ + + printk("Set the subsystem vendor id\n"); + pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086); + + printk("Disabling pm stuff in pci config space\n"); + +#define MAX_COUNTERS +#ifndef MAX_COUNTERS + /* counters to 0 */ +#define WHICH_COUNTERS(min,max) min +#else + /* max out the counters */ +#define WHICH_COUNTERS(min,max) max +#endif + + /* CNTA */ + pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF)); + + /* CNTB */ + pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df)); + + /* GPICTL */ + pci_write_config_dword(pm_pcidev, 0x4c, 0); + + /* DEVRESD */ + pci_write_config_dword(pm_pcidev, 0x50, 0); + + /* DEVACTA */ + pci_write_config_dword(pm_pcidev, 0x54, 0); + + /* DEVACTB */ + pci_write_config_dword(pm_pcidev, 0x58, 0); + + /* DEVRESA */ + pci_write_config_dword(pm_pcidev, 0x5c, 0); + + /* DEVRESB */ + pci_write_config_dword(pm_pcidev, 0x60, 0); + + /* DEVRESC */ + pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */ + + /* DEVRESE */ + pci_write_config_dword(pm_pcidev, 0x68, 0); + + /* DEVRESF */ + pci_write_config_dword(pm_pcidev, 0x6c, 0); + + /* DEVRESG */ + pci_write_config_dword(pm_pcidev, 0x70, 0); + + /* DEVRESH */ + pci_write_config_dword(pm_pcidev, 0x74, 0); + + /* DEVRESI */ + pci_write_config_dword(pm_pcidev, 0x78, 0); + + /* DEVRESJ */ + pci_write_config_dword(pm_pcidev, 0x7c, 0); + +#endif + +#if 1 + + /* Verify that smi is disabled */ + printk("Testing SMI\r\n"); + { + u32 value; + pci_read_config_dword(pm_pcidev, 0x58, &value); + pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25)); + } + outb(inb(0xb2), 0xb2); + printk("SMI disabled\r\n"); +#endif +#if 0 + + for(i = 0; i < 255; i++) { + printk("%08x\r\n", i); + __rdtsc_delay2(1000000000UL, pm_io); + } +#endif +} diff --git a/src/superio/SMC/fdc37c669/setup_serial.inc b/src/superio/SMC/fdc37c669/setup_serial.inc new file mode 100644 index 0000000000..a0e7787b02 --- /dev/null +++ b/src/superio/SMC/fdc37c669/setup_serial.inc @@ -0,0 +1,96 @@ +/* + * Enable the peripheral devices on the FDC37N769 Super IO chip + */ + +/* + * This code is untested but should at least get a serial port working. + * -Tyson + */ + +/* The base address is either 0x3F0 or 0x370, depending on config pin */ + +#ifndef SMC_BASE +#error SMC_BASE must be defined as 0x3F0 or 0x370 +#endif + +#if (SMC_BASE == 0x370) +/* #warning SMC_BASE set to 0x370 */ +#elif (SMC_BASE == 0x3f0) +/* #warning SMC_BASE set to 0x3f0 */ +#else +#error SMC_BASE defined as other than 0x3F0 or 0x370 +#endif + +#define SMC_INDEX SMC_BASE +#define SMC_DATA SMC_BASE+1 + +#define SMC_READ(index) \ + mov index, %al ; \ + mov $SMC_BASE, %dx ; \ + outb %al, %dx ; \ + inc %dx ; \ + inb %dx, %al ; + +#define SMC_WRITE(data, index) \ + mov data, %ah ; \ + mov index, %al ; \ + mov $SMC_BASE, %dx ; \ + outb %al, %dx ; \ + inc %dx ; \ + mov %ah, %al ; \ + outb %al, %dx ; + + + /* Enter the configuration state */ + + mov $0x55, %al + mov $SMC_BASE, %dx + outb %al, %dx + + /* Check for Device ID */ + + SMC_READ($0x0d) + cmp %al, 0x04 + je 2f + mov $0xfe, %al + outb %al, $0x80 +#if 0 +1: hlt + jmp 1b +#endif +2: + + /* Pin configuration - need to enable IRQ 4 output */ + + SMC_WRITE($0xf4, $0x03) ; + + SMC_WRITE($0x88, $0x02) ; + + /* Set address of parallel port */ +#if 0 + SMC_WRITE($0xde, $0x23) ; +#endif + /* Set address of serial port 0 */ + + SMC_WRITE($0xfe, $0x24) ; + + /* Set address of serial port 1 */ + + SMC_WRITE($0xbe, $0x25) ; + + /* Set IRQs of serial ports */ + + SMC_WRITE($0x21, $0x28) ; + + /* Set valid bit */ + + SMC_READ($0x00) + or $0x80, %al + SMC_WRITE(%al, $0x00) + + /* Exit the configuration state */ + + mov $0xAA, %al + mov $SMC_BASE, %dx + outb %al, %dx + diff --git a/src/superio/SMC/fdc37c669/superio.c b/src/superio/SMC/fdc37c669/superio.c new file mode 100644 index 0000000000..e49e6786c2 --- /dev/null +++ b/src/superio/SMC/fdc37c669/superio.c @@ -0,0 +1,215 @@ +#include +#include + +#define PNP_COM1_DEVICE 0x03 +#define PNP_COM2_DEVICE 0x03 +/* + * This file is for setting up the SMC Super IO chip. + * + * This file contains some hard coded mappings for IRQs which may + * work for most boards but is really board specific. A + * configuration mechanism is needed. + * + * I have only implemented the UART features that I needed at + * the time plus enableing EPP mode to get interrupts that can + * be shared. Other features for floppies and parallel ports + * can be added by others as needed. + * + * -Tyson Sawyer tyson@rwii.com + * + * Sharing interrupts between two SMC chips doesn't work for me. -tds + */ + +static int smc_configuration_state(int addr, int state) { + + if ((addr!=0x370) && (addr!=0x3f0)) return(-1); + + if (state) { + outb(0x55, addr); + return(0); + } + else { + outb(0xAA, addr); + return(0); + } + + return(-1); +} + +static int smc_write(int addr, unsigned char data, unsigned char index) { + + if ((addr!=0x370) && (addr!=0x3f0)) return(-1); + + outb(index, addr); + outb(data, addr+1); + return(0); +} + +static int smc_read(int addr, unsigned char index, unsigned char *data) { + + if ((addr!=0x370) && (addr!=0x3f0)) return(-1); + + outb(index, addr); + *data = inb(addr+1); + return(0); +} + +int smc_uart_setup(int addr, + int addr1, int irq1, + int addr2, int irq2) { + + int rv; + unsigned char int1, int2; + unsigned char data; + + if ((addr!=0x370) && (addr!=0x3f0)) return(-1); + + /* + * Warning: + * Board specifc mapping of IRQs here. + * A configuration mechanism is needed. + */ + + switch (irq1) { + case 3: int1 = 1; break; + case 4: int1 = 2; break; + case 5: int1 = 3; break; + case 6: int1 = 4; break; + case 7: int1 = 5; break; + case 10: int1 = 6; break; + case 11: int1 = 8; break; + default: int1 = 0; + } + + switch (irq2) { + case 3: int2 = 1; break; + case 4: int2 = 2; break; + case 5: int2 = 3; break; + case 6: int2 = 4; break; + case 7: int2 = 5; break; + case 10: int2 = 6; break; + case 11: int2 = 8; break; + default: int2 = 0; + } + + if (int1 == int2) { + int2 = 0x0f; + } + + rv = smc_configuration_state(addr, 1); if (rv) return(rv); + rv = smc_write(addr, (addr1>>2) & 0xfe, 0x24); if (rv) return(rv); + rv = smc_write(addr, (addr2>>2) & 0xfe, 0x25); if (rv) return(rv); + rv = smc_write(addr, (int1<<4) | int2, 0x28); if (rv) return(rv); + + /* Enable INTB output */ + + if ((int1==2) || (int2==2)) { + rv = smc_read(addr, 0x03, &data); if (rv) return(rv); + rv = smc_write(addr, data | 0x84, 0x03); if (rv) return(rv); + } + + rv = smc_configuration_state(addr, 0); return(rv); +} + +int smc_pp_setup(int addr, int pp_addr, int mode) { + int rv; + unsigned char data; + + rv = smc_configuration_state(addr, 1); if (rv) return(rv); + + rv = smc_read(addr, 0x04, &data); if (rv) return(rv); + data = (data & (~0x03)) | (mode & 0x03); + rv = smc_write(addr, data, 0x04); if (rv) return(rv); + + rv = smc_read(addr, 0x01, &data); if (rv) return(rv); + data = data & (~0x08); + rv = smc_write(addr, data, 0x01); if (rv) return(rv); + + rv = smc_write(addr, (pp_addr>>2) & 0xff, 0x23); if (rv) return(rv); + + rv = smc_configuration_state(addr, 0); return(rv); +} + +int smc_validbit(int addr, int valid) { + int rv; + unsigned char data; + + if ((addr!=0x370) && (addr!=0x3f0)) return(-1); + + rv = smc_configuration_state(addr, 1); if (rv) return(rv); + rv = smc_read(addr, 0x00, &data); if (rv) return(rv); + + if (valid) { + data = data | 0x80; + } + else { + data = data & (~0x80); + } + + rv = smc_write(addr, data, 0x00); if (rv) return(rv); + rv = smc_configuration_state(addr, 0); return(rv); +} + +/* + * ============== Linux bios standard superio functions ======== + * + * These functions suck. + */ + +void +enter_pnp() +{ + // unlock it XXX make this a subr at some point + // outb(0x87, PNPADDR); + // outb(0x87, PNPADDR); +} + +void +exit_pnp() +{ + /* all done. */ + // select configure control + // outb(0xaa, PNPADDR); +} + +#ifdef MUST_ENABLE_FLOPPY + +void enable_floppy() +{ + /* now set the LDN to floppy LDN */ +// outb(0x7, PNPADDR); /* pick reg. 7 */ +// outb(0x0, PNPDATA); /* LDN 0 to reg. 7 */ + + /* now select register 0x30, and set bit 1 in that register */ +// outb(0x30, PNPADDR); +// outb(0x1, PNPDATA); +} +#endif /* MUST_ENABLE_FLOPPY */ + +void +enable_com(int com) +{ + // unsigned char b; + /* now set the LDN to com LDN */ + // outb(0x7, PNPADDR); /* pick reg. 7 */ + // outb(com, PNPDATA); /* LDN 0 to reg. 7 */ + + /* now select register 0x30, and set bit 1 in that register */ + // outb(0x30, PNPADDR); + // outb(0x1, PNPDATA); + +} + +void +final_superio_fixup() +{ + + enter_pnp(); +#ifdef MUST_ENABLE_FLOPPY + enable_floppy(); +#endif + enable_com(PNP_COM1_DEVICE); + enable_com(PNP_COM2_DEVICE); + + exit_pnp(); +} diff --git a/src/superio/SMC/fdc37c669/superio.h b/src/superio/SMC/fdc37c669/superio.h new file mode 100644 index 0000000000..a5b680181e --- /dev/null +++ b/src/superio/SMC/fdc37c669/superio.h @@ -0,0 +1,17 @@ +#ifndef _SMC_SUPER_IO_H_ +#define _SMC_SUPER_IO_H_ + +#define SMC_PP_MODE_SPP 0x00 +#define SMC_PP_MODE_EPP_SPP 0x01 +#define SMC_PP_MODE_ECP 0x02 +#define SMC_PP_MODE_EPP_ECP 0x03 + +int smc_uart_setup(int smc_addr, + int addr1, int irq1, + int addr2, int irq2); + +int smc_pp_setup(int smc_addr, int pp_addr, int mode); + +int smc_validbit(int smc_addr, int valid); + +#endif /* _SMC_SUPER_IO_H_ */ diff --git a/util/config/l440bx-test12.config b/util/config/l440bx-test12.config new file mode 100644 index 0000000000..e11474501a --- /dev/null +++ b/util/config/l440bx-test12.config @@ -0,0 +1,34 @@ +# This will make a target directory of ./winfast +# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE +# CONFIG TOOL. Make it absolute if you like +arch i386 +target /tmp/fbios/l440bx + +mainboard intel/l440bx + +# Enable Serial Console for debugging +# It will come up at 115200,8n1 +option SERIAL_CONSOLE + +# Enable MicroCode update and L2 Cache init for PII and PIII +option UPDATE_MICROCODE +option CONFIGURE_L2_CACHE + +# Use the internal VGA frame buffer device +#option HAVE_FRAMEBUFFER +option USE_CACHE_RAM=0 +option USE_GENERIC_ROM=1 +option USE_ELF_BOOT=0 + +#makedefine PHLASH_BASE_NAME=p13-0125 +#makedefine BOOT_IMAGE=/tftpboot/netboot.ebi +makedefine BOOT_IMAGE=vmlinux.bin.gz.block + +# Path to your kernel (vmlinux) +# NOTE; you need a path to your test12 kernel here. +linux /manpreet/freebios/linux + +# Kernel command line parameters +#commandline ro panic=5 root=/dev/hda5 console=ttyS0,115200 debug 3 + +