From 575ca7374c546e969e81402b339408e703c742f8 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 4 Feb 2008 16:16:16 +0000 Subject: [PATCH] This change moves the geodelxinit code from stage2 to stage1, which in turn gets cache turned on much sooner. The system boots a bit faster. We're still far too slow, perhaps because we are not caching ROM? Index: arch/x86/Makefile Add ../../northbridge/amd/geodelx/geodelxinit.o object Index: arch/x86/geodelx/geodelxinit.c add sizeram function. Index: arch/x86/geodelx/stage1.c add called to northbridge_init_early() Index: northbridge/amd/geodelx/Makefile remove geodelxinit.o object Index: northbridge/amd/geodelx/geodelx.c remove call to northbridge_init_early() remove sizeram function. Signed-off-by: Ronald G. Minnich Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://coreboot.org/repository/coreboot-v3@572 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- arch/x86/Makefile | 1 + arch/x86/geodelx/stage1.c | 2 ++ northbridge/amd/geodelx/Makefile | 1 - northbridge/amd/geodelx/geodelx.c | 45 +-------------------------- northbridge/amd/geodelx/geodelxinit.c | 44 +++++++++++++++++++++++++- 5 files changed, 47 insertions(+), 46 deletions(-) diff --git a/arch/x86/Makefile b/arch/x86/Makefile index a30caf71fd..bff4210f49 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -117,6 +117,7 @@ else ifeq ($(CONFIG_CPU_AMD_GEODELX),y) STAGE0_CAR_OBJ = geodelx/stage0.o STAGE0_ARCH_X86_OBJ += geodelx/stage1.o + STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o else STAGE0_CAR_OBJ = stage0_i586.o endif diff --git a/arch/x86/geodelx/stage1.c b/arch/x86/geodelx/stage1.c index f4c6ae6448..0c4a54b519 100644 --- a/arch/x86/geodelx/stage1.c +++ b/arch/x86/geodelx/stage1.c @@ -55,6 +55,7 @@ void geodelx_msr_init(void) */ void disable_car(void) { + extern void northbridge_init_early(void); int i; for (i = 0; i < ARRAY_SIZE(msr_table); i++) @@ -67,5 +68,6 @@ void disable_car(void) __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); __asm__ __volatile__ ("wbinvd\n"); banner(BIOS_DEBUG, "Disable_car: done wbinvd"); + northbridge_init_early(); banner(BIOS_DEBUG, "disable_car: done"); } diff --git a/northbridge/amd/geodelx/Makefile b/northbridge/amd/geodelx/Makefile index 73eb65617f..0a555ac721 100644 --- a/northbridge/amd/geodelx/Makefile +++ b/northbridge/amd/geodelx/Makefile @@ -22,7 +22,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y) STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \ - $(obj)/northbridge/amd/geodelx/geodelxinit.o \ $(obj)/northbridge/amd/geodelx/vsmsetup.o endif diff --git a/northbridge/amd/geodelx/geodelx.c b/northbridge/amd/geodelx/geodelx.c index c95912da0b..4d8291035b 100644 --- a/northbridge/amd/geodelx/geodelx.c +++ b/northbridge/amd/geodelx/geodelx.c @@ -141,49 +141,6 @@ static const struct msrinit msr_defaults[] = { {0}, }; -/** - * Size up ram. - * - * All we need to do here is read the MSR for DRAM and grab out the sizing - * bits. Note that this code depends on initram having run. It uses the MSRs, - * not the SPDs, and the MSRs of course are set up by initram. - * - * @return TODO - */ -int sizeram(void) -{ - struct msr msr; - int sizem = 0; - u32 dimm; - - /* Get the RAM size from the memory controller as calculated - * and set by auto_size_dimm(). - */ - msr = rdmsr(MC_CF07_DATA); - printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, - msr.lo); - - /* DIMM 0 */ - dimm = msr.hi; - /* Installed? */ - if ((dimm & 7) != 7) { - /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ - sizem = 4 << ((dimm >> 12) & 0x0F); - } - - /* DIMM 1 */ - dimm = msr.hi >> 16; - /* Installed? */ - if ((dimm & 7) != 7) { - /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ - sizem += 4 << ((dimm >> 12) & 0x0F); - } - - printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem); - - return sizem; -} - /** * Currently not set up. * @@ -317,7 +274,7 @@ static void geodelx_pci_domain_phase2(struct device *dev) printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - northbridge_init_early(); +// northbridge_init_early(); chipsetinit(); setup_realmode_idt(); diff --git a/northbridge/amd/geodelx/geodelxinit.c b/northbridge/amd/geodelx/geodelxinit.c index d3295885e8..6df94fa0e7 100644 --- a/northbridge/amd/geodelx/geodelxinit.c +++ b/northbridge/amd/geodelx/geodelxinit.c @@ -25,7 +25,6 @@ #include /* Function prototypes */ -extern int sizeram(void); struct gliutable { unsigned long desc_name; @@ -141,6 +140,49 @@ static void ShadowInit(struct gliutable *gl) writeglmsr(gl); } +/** + * Size up ram. + * + * All we need to do here is read the MSR for DRAM and grab out the sizing + * bits. Note that this code depends on initram having run. It uses the MSRs, + * not the SPDs, and the MSRs of course are set up by initram. + * + * @return TODO + */ +int sizeram(void) +{ + struct msr msr; + int sizem = 0; + u32 dimm; + + /* Get the RAM size from the memory controller as calculated + * and set by auto_size_dimm(). + */ + msr = rdmsr(MC_CF07_DATA); + printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, + msr.lo); + + /* DIMM 0 */ + dimm = msr.hi; + /* Installed? */ + if ((dimm & 7) != 7) { + /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ + sizem = 4 << ((dimm >> 12) & 0x0F); + } + + /* DIMM 1 */ + dimm = msr.hi >> 16; + /* Installed? */ + if ((dimm & 7) != 7) { + /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ + sizem += 4 << ((dimm >> 12) & 0x0F); + } + + printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem); + + return sizem; +} + /** * Set up the system memory registers, i.e. memory that can be used * for non-VSM (or SMM) purposes.