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mb/google/rex/var/kanix: Add LAN RTL8125BG related settings

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Add LAN RTL8125BG related settings based on schematic(ver.1122A).

BUG=b:380218793, b:366291025
TEST=emerge-rex coreboot pass

Change-Id: Icc24f00406d5f91e38725588109c61b7bad099c3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85322
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tyler Wang 2024-11-26 16:40:10 +08:00 • committed by Subrata Banik
commit 57346fadf5
3 changed files with 22 additions and 2 deletions
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3
src/mainboard/google/rex/Kconfig
View file

@ -71,6 +71,9 @@ config BOARD_GOOGLE_MODEL_KANIX
def_bool n
select BOARD_GOOGLE_BASEBOARD_REX
select DRIVERS_GENERIC_ALC1015
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
select SOC_INTEL_CSE_SEND_EOP_ASYNC

4
src/mainboard/google/rex/variants/kanix/gpio.c
View file

@ -195,8 +195,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG),
/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E04 : [] ==> SOC_PEN_DETECT, test point */
PAD_NC(GPP_E04, NONE),
/* GPP_E04 : [] ==> SOC_WAKE_L ==> LAN_WAKE_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_E04, NONE, DEEP, EDGE_SINGLE),
/* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */
PAD_CFG_GPO(GPP_E05, 1, DEEP),
/* GPP_E06 : GPP_E06_STRAP ==> Component NC */

17
src/mainboard/google/rex/variants/kanix/overridetree.cb
View file

@ -552,6 +552,23 @@ chip soc/intel/meteorlake
device generic 0 on end
end
end #PCIE5 WLAN card
device ref pcie_rp6 on
chip drivers/net
register "wake" = "GPE0_DW1_04"
register "led_feature" = "0xe0"
register "customized_led0" = "0x23f"
register "customized_led2" = "0x028"
register "enable_aspm_l1_2" = "1"
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
# Enable PCIE 6 using clk 6
register "pcie_rp[PCH_RP(6)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end # RTL8125 Ethernet NIC
device ref gspi1 on
chip drivers/spi/acpi
register "name" = ""CRFP""