From 56cfebb9c0a81fc8b8e9fa241f8582e6c0c72328 Mon Sep 17 00:00:00 2001 From: huang lin Date: Thu, 29 Jan 2015 19:50:59 +0800 Subject: [PATCH] rk3288: move reboot_from_watchdog() before rk808 setting we will use dvs to adjust the voltage in kernel, if device reset by watchdog in kernel, the dvs gpio may not reset, and we use the i2c to adjust rk808 voltage in coreboot, so it may failure. so we move the reboot_from_watchdog() before the rk808 setting. BUG=None TEST=Boot from speedy BRANCH=None Change-Id: I92b5c6413bbffe30566178de89df1f9683790982 Signed-off-by: huang lin Reviewed-on: https://chromium-review.googlesource.com/244289 Reviewed-by: Julius Werner Commit-Queue: Julius Werner Tested-by: Julius Werner (cherry picked from commit 76efb4b0196eecc84664a4c5dce2221152a39c0a) Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/245494 --- src/mainboard/google/veyron_gus/bootblock.c | 6 +++--- src/mainboard/google/veyron_jaq/bootblock.c | 6 +++--- src/mainboard/google/veyron_jerry/bootblock.c | 6 +++--- src/mainboard/google/veyron_mighty/bootblock.c | 6 +++--- src/mainboard/google/veyron_minnie/bootblock.c | 6 +++--- src/mainboard/google/veyron_pinky/bootblock.c | 6 +++--- src/mainboard/google/veyron_speedy/bootblock.c | 6 +++--- 7 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/veyron_gus/bootblock.c b/src/mainboard/google/veyron_gus/bootblock.c index acf81bc0cb..2f012ec80e 100644 --- a/src/mainboard/google/veyron_gus/bootblock.c +++ b/src/mainboard/google/veyron_gus/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,9 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_jaq/bootblock.c b/src/mainboard/google/veyron_jaq/bootblock.c index acf81bc0cb..2f012ec80e 100644 --- a/src/mainboard/google/veyron_jaq/bootblock.c +++ b/src/mainboard/google/veyron_jaq/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,9 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c index acf81bc0cb..2f012ec80e 100644 --- a/src/mainboard/google/veyron_jerry/bootblock.c +++ b/src/mainboard/google/veyron_jerry/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,9 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c index acf81bc0cb..2f012ec80e 100644 --- a/src/mainboard/google/veyron_mighty/bootblock.c +++ b/src/mainboard/google/veyron_mighty/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,9 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_minnie/bootblock.c b/src/mainboard/google/veyron_minnie/bootblock.c index acf81bc0cb..2f012ec80e 100644 --- a/src/mainboard/google/veyron_minnie/bootblock.c +++ b/src/mainboard/google/veyron_minnie/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,9 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index acf81bc0cb..2f012ec80e 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,9 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c index acf81bc0cb..2f012ec80e 100644 --- a/src/mainboard/google/veyron_speedy/bootblock.c +++ b/src/mainboard/google/veyron_speedy/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,9 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz);