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src/include: Drop unneeded empty lines

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Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS 2020-08-19 21:51:55 +02:00 • committed by Patrick Georgi
commit 563fc0889f
27 changed files with 0 additions and 39 deletions
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1
src/include/device/dram/ddr3.h
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@ -19,7 +19,6 @@
#include <device/dram/common.h>
#include <types.h>
/**
* Convenience definitions for SPD offsets
*

1
src/include/device/dram/ddr4.h
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@ -21,7 +21,6 @@
#define SPD_DDR4_PART_OFF 329
#define SPD_DDR4_PART_LEN 20
/*
* Module type (byte 3, bits 3:0) of SPD
* This definition is specific to DDR4. DDR2/3 SPDs have a different structure.

1
src/include/device/hypertransport_def.h
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@ -18,7 +18,6 @@
#define HT_FREQ_2600Mhz 14
#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */
static inline bool offset_unit_id(bool is_sb_ht_chain)
{
bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)

1
src/include/device/path.h
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@ -137,7 +137,6 @@ struct device_path {
};
};
#define DEVICE_PATH_MAX 40
#define BUS_PATH_MAX (DEVICE_PATH_MAX+10)

2
src/include/device/pci_def.h
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@ -305,7 +305,6 @@
#define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
@ -521,7 +520,6 @@
#define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded

2
src/include/device/pci_ids.h
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@ -517,7 +517,6 @@
#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505
#define PCI_DEVICE_ID_NS_87410 0xd001
#define PCI_VENDOR_ID_TSENG 0x100c
#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202
#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205
@ -1664,7 +1663,6 @@
#define PCI_DEVICE_ID_ATT_L56XMF 0x0440
#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480
#define PCI_VENDOR_ID_SPECIALIX 0x11cb
#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000
#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000

1
src/include/device/pci_mmio_cfg.h
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@ -7,7 +7,6 @@
#include <device/mmio.h>
#include <device/pci_type.h>
/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
* prevent some sub-optimal constant folding. */
extern u8 *const pci_mmconf;

1
src/include/device/pnp.h
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@ -67,7 +67,6 @@ struct resource *pnp_get_resource(struct device *dev, unsigned int index);
void pnp_enable_devices(struct device *dev, struct device_operations *ops,
unsigned int functions, struct pnp_info *info);
struct pnp_mode_ops {
void (*enter_conf_mode)(struct device *dev);
void (*exit_conf_mode)(struct device *dev);

1
src/include/device/resource.h
View file

@ -109,7 +109,6 @@ static inline void *res2mmio(struct resource *res, unsigned long offset,
const struct device *largest_resource(struct bus *bus, struct resource **result_res,
unsigned long type_mask, unsigned long type);
/* Compute and allocate resources. This is the main resource allocator entry point. */
void allocate_resources(const struct device *root);