erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

src/include: Drop unneeded empty lines

Browse source 
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS 2020-08-19 21:51:55 +02:00 • committed by Patrick Georgi
commit 563fc0889f
27 changed files with 0 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/include/cpu/x86/msr.h
View file

@ -299,7 +299,6 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
return MCA_ERRTYPE_UNKNOWN;
}
/* Helper for setting single MSR bits */
static inline void msr_set_bit(unsigned int reg, unsigned int bit)
{
@ -318,6 +317,5 @@ static inline void msr_set_bit(unsigned int reg, unsigned int bit)
wrmsr(reg, msr);
}
#endif /* __ASSEMBLER__ */
#endif /* CPU_X86_MSR_H */

1
src/include/cpu/x86/mtrr.h
View file

@ -27,7 +27,6 @@
#define MTRR_DEF_TYPE_EN (1 << 11)
#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
#define IA32_SMRR_PHYS_BASE 0x1f2
#define IA32_SMRR_PHYS_MASK 0x1f3
#define SMRR_PHYS_MASK_LOCK (1 << 10)

1
src/include/cpu/x86/post_code.h
View file

@ -3,7 +3,6 @@
#include <console/post_codes.h>
#if CONFIG(POST_IO)
#define post_code(value) \
movb $value, %al; \