src/include: Drop unneeded empty lines

Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/include/cpu/intel/em64t100_save_state.h

@@ -66,7 +66,6 @@ typedef struct {
 	u64	rsi;
 	u64	rdi;
 
-
 	u64	io_mem_addr;
 	u32	io_misc_info;
 

src/include/cpu/intel/em64t101_save_state.h

@@ -6,7 +6,6 @@
 #include <types.h>
 #include <cpu/x86/smm.h>
 
-
 /* Intel Revision 30101 SMM State-Save Area
  * The following processor architectures use this:
  * - Westmere
@@ -83,7 +82,6 @@ typedef struct {
 	u64	rsi;
 	u64	rdi;
 
-
 	u64	io_mem_addr;
 	u32	io_misc_info;
 

src/include/cpu/intel/smm_reloc.h

@@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_
 
 bool cpu_has_alternative_smrr(void);
 
-
 #define MSR_PRMRR_PHYS_BASE 0x1f4
 #define MSR_PRMRR_PHYS_MASK 0x1f5
 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4

src/include/cpu/intel/speedstep.h

@@ -18,7 +18,6 @@
  */
 #define PMB1_BASE 0x800
 
-
 /* Speedstep related MSRs */
 #define MSR_THERM2_CTL		0x19D
 #define MSR_EBC_FREQUENCY_ID	0x2c