mb/google/nissa/var/glassway: Add initial LTE related settings
1. Add DB_1C_LTE 4 on DB_USB fw_config.
2. Implement WWAN power sequencing.
3. Disable LTE-related GPIOs based on fw_config.
4. Add I2C SX9324 (P-sensor) support.
Refer Schematic file: CA31AC_R10_MB_SUB_240903A_P.pdf
BUG=b:374666995
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Confirm the device node i2c-STH9324:00 created correctly,
and command for # i2cdump -f -y 11 0x28 is workable.
Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84925
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Daniel Peng
Eric Lai
parent
01dfc9b187
commit
55e7baff92
4 changed files with 117 additions and 4 deletions
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@ -278,7 +278,10 @@ config BOARD_GOOGLE_GLASSWAY
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENESYSLOGIC_GL9750
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select DRIVERS_I2C_SX9324
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select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
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select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
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select HAVE_WWAN_POWER_SEQUENCE
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select INTEL_GMA_HAVE_VBT
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config BOARD_GOOGLE_GOTHRAX
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@ -5,6 +5,19 @@
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#include <console/console.h>
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#include <fw_config.h>
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static const struct pad_config lte_disable_pads[] = {
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/* A8 : WWAN_RF_DISABLE_ODL */
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PAD_NC(GPP_A8, NONE),
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/* D6 : WWAN_EN */
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PAD_NC(GPP_D6, NONE),
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/* F12 : WWAN_RST_L */
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PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
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/* H19 : SOC_I2C_SUB_INT_ODL */
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PAD_NC(GPP_H19, NONE),
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/* H23 : WWAN_SAR_DETECT_ODL */
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PAD_NC(GPP_H23, NONE),
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};
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static const struct pad_config stylus_disable_pads[] = {
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/* F13 : SOC_PEN_DETECT_R_ODL */
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PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
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@ -14,6 +27,12 @@ static const struct pad_config stylus_disable_pads[] = {
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void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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{
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if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
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printk(BIOS_INFO, "Disable LTE-related GPIO pins on Glassway serial projects.\n");
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gpio_padbased_override(padbased_table, lte_disable_pads,
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ARRAY_SIZE(lte_disable_pads));
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}
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if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
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printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
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gpio_padbased_override(padbased_table, stylus_disable_pads,
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@ -5,4 +5,8 @@
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#include <baseboard/gpio.h>
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#define WWAN_FCPO GPP_D6
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#define WWAN_RST GPP_F12
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#define T2_OFF_MS 20
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#endif
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@ -8,10 +8,11 @@ fw_config
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option AUDIO_ALC5650_ALC5650 1
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end
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field DB_USB 5 7
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option DB_NONE 0
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option DB_1C 1
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option DB_1A 2
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option DB_1C_1A 3
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option DB_NONE 0
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option DB_1C 1
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option DB_1A 2
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option DB_1C_1A 3
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option DB_1C_LTE 4
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end
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field SD_CARD 8
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option SD_ABSENT 0
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@ -426,6 +427,78 @@ chip soc/intel/alderlake
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end
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end
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end #I2C1
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device ref i2c2 on
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chip drivers/i2c/sx9324
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register "desc" = ""SAR Proximity Sensor""
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
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register "speed" = "I2C_SPEED_FAST"
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register "uid" = "1"
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register "reg_gnrl_ctrl0" = "0x16"
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register "reg_gnrl_ctrl1" = "0x21"
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register "reg_afe_ctrl0" = "0x20"
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register "reg_afe_ctrl3" = "0x00"
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register "reg_afe_ctrl4" = "0x46"
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register "reg_afe_ctrl6" = "0x00"
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register "reg_afe_ctrl7" = "0x46"
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register "reg_afe_ph0" = "0x3d"
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register "reg_afe_ph1" = "0x1b"
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register "reg_afe_ph2" = "0x1f"
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register "reg_afe_ph3" = "0x3d"
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register "reg_afe_ctrl8" = "0x12"
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register "reg_afe_ctrl9" = "0x08"
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register "reg_prox_ctrl0" = "0x0b"
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register "reg_prox_ctrl1" = "0x0b"
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register "reg_prox_ctrl2" = "0x20"
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register "reg_prox_ctrl3" = "0x20"
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register "reg_prox_ctrl4" = "0x0c"
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register "reg_prox_ctrl5" = "0x00"
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register "reg_prox_ctrl6" = "0x20"
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register "reg_prox_ctrl7" = "0xc0"
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register "reg_adv_ctrl0" = "0x00"
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register "reg_adv_ctrl1" = "0x00"
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register "reg_adv_ctrl2" = "0x00"
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register "reg_adv_ctrl3" = "0x00"
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register "reg_adv_ctrl4" = "0x00"
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register "reg_adv_ctrl5" = "0x05"
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register "reg_adv_ctrl6" = "0x00"
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register "reg_adv_ctrl7" = "0x00"
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register "reg_adv_ctrl8" = "0x00"
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register "reg_adv_ctrl9" = "0x00"
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register "reg_adv_ctrl10" = "0x00"
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register "reg_adv_ctrl11" = "0x00"
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register "reg_adv_ctrl12" = "0x00"
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register "reg_adv_ctrl13" = "0x00"
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register "reg_adv_ctrl14" = "0x80"
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register "reg_adv_ctrl15" = "0x0c"
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register "reg_adv_ctrl16" = "0x04"
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register "reg_adv_ctrl17" = "0x70"
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register "reg_adv_ctrl18" = "0x20"
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register "reg_adv_ctrl19" = "0x00"
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register "reg_adv_ctrl20" = "0x00"
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register "reg_irq_msk" = "0x60"
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register "reg_irq_cfg0" = "0x00"
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register "reg_irq_cfg1" = "0x80"
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register "reg_irq_cfg2" = "0x00"
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register "ph0_pin" = "{1, 3, 3}"
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register "ph1_pin" = "{3, 2, 1}"
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register "ph2_pin" = "{3, 3, 1}"
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register "ph3_pin" = "{1, 3, 3}"
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register "ph01_resolution" = "512"
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register "ph23_resolution" = "512"
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register "startup_sensor" = "1"
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register "ph01_proxraw_strength" = "3"
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register "ph23_proxraw_strength" = "3"
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register "avg_pos_strength" = "256"
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register "cs_idle_sleep" = ""gnd""
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register "int_comp_resistor" = ""lowest""
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register "input_precharge_resistor_ohms" = "4000"
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register "input_analog_gain" = "1"
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device i2c 28 on
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probe DB_USB DB_1C_LTE
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end
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end
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end #I2C2
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device ref i2c3 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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@ -597,6 +670,13 @@ chip soc/intel/alderlake
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probe DB_USB DB_1C_1A
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end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 WWAN""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port4 on
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probe DB_USB DB_1C_LTE
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end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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@ -632,6 +712,13 @@ chip soc/intel/alderlake
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probe DB_USB DB_1C_1A
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end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 WWAN""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb3_port2 on
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probe DB_USB DB_1C_LTE
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end
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end
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end
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end
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end
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