From 55afbe250d3174f2f58bf8b28e323f6fd230351b Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 30 Apr 2025 12:48:38 -0500 Subject: [PATCH] soc/intel/elkhartlake: Hook up S0ix setting to option API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hook up the s0ix_enable setting to the option API, so it can be changed at runtime without recompilation. Default to the value set by the mainboard. Change-Id: I2d2f5c1587bd86c8fee634a49e1ec989c2bef783 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/87499 Reviewed-by: Jérémy Compostella Reviewed-by: Sean Rhodes Tested-by: build bot (Jenkins) --- src/soc/intel/elkhartlake/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 2f2e7408c4..082acaf7ae 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -505,6 +505,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); + + /* Runtime configuration of S0ix */ + config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable); } /* Mainboard GPIO Configuration */