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rockchip/rk3399: Change 933 DPLL to low jitter rate

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This changes the 933 DPLL rate to 928 which has low jitter.

BRANCH=none
BUG=chrome-os-partner:57845
TEST=boot kevin and run
while true; do sleep 0.1; memtester 500K 1 > /dev/null; done
for several hours

Change-Id: Iaa12bf67527b6d0e809657c513b8d1c66af25174
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404550
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Derek Basehore 2016-10-27 13:51:49 -07:00 • committed by chrome-bot
commit 54ebf8763b
1 changed files with 1 additions and 1 deletions
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2
src/soc/rockchip/rk3399/clock.c
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@ -557,7 +557,7 @@ void rkclk_configure_ddr(unsigned int hz)
break;
case 933*MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1};
{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
break;
default:
die("Unsupported SDRAM frequency, add to clock.c!");