From 54e1a439c0e29aaf4fc542ae756f7bb036ceaf3e Mon Sep 17 00:00:00 2001 From: Dailunxue Date: Wed, 3 Dec 2014 16:03:23 +0800 Subject: [PATCH] rk3288: Increase the delay to 10us when DDR revoked reset. After DDR PHY reset de-asserted, DLL automatically starts to lock, and the lock time is maximum 5.12us. The output clock of DLL supplies the clocks of DDR controller and PHY digital logic. So before DLL lock, the clocks of DDR controller and PHY digital logic are indeterminate. When programming DDR in the period of DLL unlock, the programming maybe unstable because of the indeterminate clocks. So we need wait for at least 5.12us after de-asserting reset, then start to program DDR registers. Add some redundancy, the waiting time hopes to achieve 10us. BUG=chrome-os-partner:33148 TEST=I'm using the following command line test ok(15000 cycles). "while sleep 4 && dut-control cold_reset:on sleep:.1 cold_reset:off; do : ; done" BRANCH=None Change-Id: I55f8cb11ed3d7962567c5f40a31e6c8aed8fdcb0 Signed-off-by: DaiLunXue Reviewed-on: https://chromium-review.googlesource.com/232894 Reviewed-by: Julius Werner Commit-Queue: Lunxue Dai Tested-by: Lunxue Dai --- src/soc/rockchip/rk3288/sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index d49b860f62..5a158adb72 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -531,7 +531,7 @@ static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs, rkclk_ddr_reset(channel, 1, 0); udelay(10); rkclk_ddr_reset(channel, 0, 0); - udelay(1); + udelay(10); } static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs,