From 543fb60ec46b855b16223ee75d7e5ac3cb9003bf Mon Sep 17 00:00:00 2001 From: Jian Tong Date: Wed, 6 Aug 2025 09:11:42 +0800 Subject: [PATCH] mb/google/brox/var/lotso: Set slew rate to 1/8 Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8. The slope of the voltage measured by the oscilloscope 4 mV/us is close to the theoretical value of 3.75 mV/us. BUG=b:404416910 TEST=emerge-brox coreboot chromeos-bootimage USE=fw_debug confirm SlowSlewRate set to 2 at FSP Change-Id: I7ec05c6a20997fcc094b20fa763eb3bc030fefa1 Signed-off-by: Jian Tong Reviewed-on: https://review.coreboot.org/c/coreboot/+/88696 Reviewed-by: Dengwu Yu Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brox/variants/lotso/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 6338e828f6..fa26f03eb9 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -74,8 +74,8 @@ chip soc/intel/alderlake # Acoustic settings register "acoustic_noise_mitigation" = "1" - register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4" - register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"