From 543dfd4461de3425a424daae6ab055663e7d1506 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 20 Jul 2016 10:30:28 -0500 Subject: [PATCH] UPSTREAM: mainboard/google/reef: handle eMMC power signal polarity change The EVT board uses an active high power control signal while the previous board used an active low signal. Update the tables to reflect the differences. BUG=chrome-os-partner:55470 BRANCH=None TEST=None Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077 Reviewed-on: https://chromium-review.googlesource.com/362345 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh --- src/mainboard/google/reef/gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 2c11adb506..d134a74b00 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -156,7 +156,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ - PAD_CFG_GPO(PMU_WAKE_B, 0, DEEP), /* EMMC_PWR_EN_N */ PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ @@ -357,6 +356,7 @@ static const struct pad_config proto_diff_table[] = { PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ + PAD_CFG_GPO(PMU_WAKE_B, 0, DEEP), /* EN_PP3300_EMMC_ODL */ }; /* Wake peripheral signals post proto. */ @@ -364,6 +364,7 @@ static const struct pad_config nonproto_diff_table[] = { PAD_CFG_GPI_SCI_LOW(GPIO_3, UP_20K, DEEP, LEVEL), /* FP_INT_L */ PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ }; #endif /* __ACPI__ */