From 543102f9e785a9564ca6e0b8642f901a6d58bfa9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 22 Apr 2017 16:48:58 +0200 Subject: [PATCH] UPSTREAM: mb/intel/d510mo: Add romstage timestamps BUG=none BRANCH=none TEST=none Change-Id: I7fab2c0634be26abb33c99d4048d31e1cebaf811 Signed-off-by: Patrick Georgi Original-Commit-Id: 0c0b79689a804bff6cba25869d810812302ff9fc Original-Change-Id: I324edce44ad82217ac1fba177f4a0bb3c799308c Original-Signed-off-by: Arthur Heymans Original-Reviewed-on: https://review.coreboot.org/19426 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Kysti Mlkki Original-Reviewed-by: Paul Menzel Reviewed-on: https://chromium-review.googlesource.com/488284 --- src/mainboard/intel/d510mo/romstage.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 1bf2b61018..c6406e6f9f 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -33,6 +33,7 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) @@ -105,6 +106,9 @@ void mainboard_romstage_entry(unsigned long bist) int s3resume = 0; int boot_path; + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (bist == 0) enable_lapic(); @@ -137,7 +141,9 @@ void mainboard_romstage_entry(unsigned long bist) } printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "Memory initialized\n"); post_code(0x31);