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UPSTREAM: mainboard/samsung/lumpy: transition away from device_t

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Replace the use of the old device_t definition inside
mainboard/samsung/lumpy.

BUG=none
BRANCH=none
TEST=none

Change-Id: I45bd8786ba4341f123264b2fbed8747447c8d4bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b542faf20
Original-Change-Id: I39fe6bad42b3b0772d09d0fa7af357b797b8e04f
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/17303
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/459660
This commit is contained in:
Antonello Dettori 2016-11-08 18:44:46 +01:00 • committed by chrome-bot
commit 53761f1ecc
1 changed files with 10 additions and 7 deletions
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17
src/mainboard/samsung/lumpy/chromeos.c
View file

@ -31,7 +31,7 @@
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
#ifndef __PRE_RAM__
#ifndef __SIMPLE_DEVICE__
#include <boot/coreboot_tables.h>
#include "ec.h"
#include <ec/smsc/mec1308/ec.h>
@ -87,10 +87,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
device_t dev;
#ifdef __PRE_RAM__
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@ -98,10 +99,11 @@ int get_write_protect_state(void)
int get_developer_mode_switch(void)
{
device_t dev;
#ifdef __PRE_RAM__
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
@ -109,10 +111,11 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void)
{
device_t dev;
#ifdef __PRE_RAM__
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;