Remove empty lines at end of file

Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;

Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/arch/arm/armv7/exception_asm.S

@@ -104,4 +104,3 @@ exception_handler:
 set_vbar:
 	mcr	p15, 0, r0, c12, c0, 0
 	bx	lr
-

src/arch/arm/armv7/timestamp.c

@@ -26,4 +26,3 @@ uint64_t timestamp_get(void)
 	timer_monotonic_get(&timestamp);
 	return (uint64_t)timestamp.microseconds;
 }
-

src/arch/arm/cpu.c

@@ -44,4 +44,3 @@ struct cpu_info *cpu_info(void)
 	addr -= sizeof(struct cpu_info);
 	return (void *)addr;
 }
-

src/arch/arm64/include/clocks.h

@@ -40,4 +40,3 @@ enum {
 	CLK_216M	= 216000000,
 	CLK_300M	= 300000000,
 };
-

src/arch/arm64/timestamp.c

@@ -26,4 +26,3 @@ uint64_t timestamp_get(void)
 	timer_monotonic_get(&timestamp);
 	return (uint64_t)timestamp.microseconds;
 }
-

src/arch/mips/ashldi3.c

@@ -57,4 +57,3 @@ long long __ashldi3(long long u, word_type b)
 
 	return w.ll;
 }
-

src/arch/riscv/include/arch/cpu.h

@@ -50,4 +50,3 @@ struct cpuinfo_riscv {
 
 struct cpu_info *cpu_info(void);
 #endif /* __ARCH_CPU_H__ */
-

src/arch/riscv/include/arch/header.ld

@@ -30,4 +30,3 @@ ENTRY(_start)
 #else
 ENTRY(stage_entry)
 #endif
-

src/arch/riscv/include/arch/hlt.h

@@ -2,5 +2,3 @@ static inline __attribute__((always_inline)) void hlt(void)
 {
         while(1);
 }
-
-

src/arch/riscv/include/arch/memlayout.h

@@ -28,4 +28,3 @@
 /* TODO: Need to add DMA_COHERENT region like on ARM? */
 
 #endif /* __ARCH_MEMLAYOUT_H */
-

src/arch/riscv/prologue.inc

@@ -19,4 +19,3 @@
 
 .section ".rom.data", "a", @progbits
 .section ".rom.text", "ax", @progbits
-

src/arch/x86/boot/wakeup.S

@@ -92,4 +92,3 @@ __wakeup_segment = RELOCATED(.)
 	.globl __wakeup_size
 __wakeup_size:
 	.long . - __wakeup
-

src/arch/x86/init/crt0_romcc_epilogue.inc

@@ -19,4 +19,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-

src/arch/x86/init/prologue.inc

@@ -21,4 +21,3 @@
 
 .section ".rom.data", "a", @progbits
 .section ".rom.text", "ax", @progbits
-

src/arch/x86/lib/timestamp.c

@@ -24,4 +24,3 @@ uint64_t timestamp_get(void)
 {
 	return rdtscll();
 }
-

src/cpu/amd/model_fxx/microcode_rev_c.h

@@ -145,5 +145,3 @@
 
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-

src/cpu/amd/model_fxx/microcode_rev_d.h

@@ -144,5 +144,3 @@
 
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-

src/cpu/amd/model_fxx/microcode_rev_e.h

@@ -145,5 +145,3 @@
 
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-

src/cpu/amd/pi/00630F01/acpi/cpu.asl

@@ -108,4 +108,3 @@
 			) {
 		}
 	} /* End _PR scope */
-

src/cpu/amd/pi/00730F01/acpi/cpu.asl

@@ -80,4 +80,3 @@
 			) {
 		}
 	} /* End _PR scope */
-

src/cpu/amd/socket_939/Kconfig

@@ -2,4 +2,3 @@ config CPU_AMD_SOCKET_939
 	bool
 	select CPU_AMD_MODEL_FXX
 	select X86_AMD_FIXED_MTRRS
-

src/cpu/amd/socket_AM2/Kconfig

@@ -10,4 +10,3 @@ config CPU_SOCKET_TYPE
 	hex
 	default 0x11
 	depends on CPU_AMD_SOCKET_AM2
-

src/cpu/amd/socket_F/Kconfig

@@ -9,4 +9,3 @@ config CPU_SOCKET_TYPE
 	hex
 	default 0x10
 	depends on CPU_AMD_SOCKET_F
-

src/cpu/intel/car/cache_as_ram.inc

@@ -368,4 +368,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-

src/cpu/intel/car/cache_as_ram_ht.inc

@@ -450,4 +450,3 @@ mtrr_table:
 	.word 0x208, 0x209, 0x20A, 0x20B
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 mtrr_table_end:
-

src/cpu/intel/fit/Kconfig

@@ -9,4 +9,3 @@ config CPU_INTEL_NUM_FIT_ENTRIES
 	depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	help
 	  This option selects the number of empty entries in the FIT table.
-

src/cpu/intel/haswell/cache_as_ram.inc

@@ -318,4 +318,3 @@ mtrr_table:
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 	.word 0x210, 0x211, 0x212, 0x213
 mtrr_table_end:
-

src/cpu/intel/model_2065x/cache_as_ram.inc

@@ -293,4 +293,3 @@ mtrr_table:
 	.word 0x26B, 0x26C, 0x26D
 	.word 0x26E, 0x26F
 mtrr_table_end:
-

src/cpu/intel/model_206ax/cache_as_ram.inc

@@ -332,4 +332,3 @@ mtrr_table:
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 	.word 0x210, 0x211, 0x212, 0x213
 mtrr_table_end:
-

src/cpu/intel/model_6ex/cache_as_ram.inc

@@ -244,4 +244,3 @@ mtrr_table:
 	.word 0x208, 0x209, 0x20A, 0x20B
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 mtrr_table_end:
-

src/cpu/intel/slot_2/Kconfig

@@ -24,4 +24,3 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
 	depends on CPU_INTEL_SLOT_2
-

src/cpu/intel/socket_PGA370/Kconfig

@@ -39,4 +39,3 @@ config DCACHE_RAM_SIZE
 	default 0x01000
 
 endif
-

src/cpu/intel/socket_mPGA604/Kconfig

@@ -29,4 +29,3 @@ config DCACHE_RAM_SIZE
 	default 0x4000
 
 endif # CPU_INTEL_SOCKET_MPGA604
-

src/cpu/ti/am335x/memlayout.ld

@@ -39,4 +39,3 @@ SECTIONS
 	}
 #endif
 }
-

src/cpu/via/car/cache_as_ram.inc

@@ -275,4 +275,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-

src/cpu/x86/16bit/entry16.inc

@@ -138,4 +138,3 @@ nullidt:
 .globl _estart
 _estart:
 	.code32
-

src/cpu/x86/32bit/entry32.inc

@@ -63,4 +63,3 @@ __protected_start:
 
 	/* Restore the BIST value to %eax */
 	movl	%ebp, %eax
-

src/cpu/x86/smm/smm_stub.S

@@ -145,4 +145,3 @@ smm_trampoline32:
 
 	/* Exit from SM mode. */
 	rsm
-

src/cpu/x86/smm/smmhandler.S

@@ -207,4 +207,3 @@ jumptable:
 	/* core 0 */
 	ljmp $0xa000, $SMM_HANDLER_OFFSET
 .align 1024, 0x00
-

src/cpu/x86/sse_enable.inc

@@ -27,4 +27,3 @@
 
 	/* Restore BIST. */
 	movl	%ebp, %eax
-

src/device/oprom/x86emu/LICENSE

@@ -14,4 +14,3 @@ know. Your code will be removed to comply with your wishes.
 If you have any questions about this, please send email to
 x86emu@linuxlabs.com or KendallB@scitechsoft.com for
 clarification.
-

src/drivers/emulation/Kconfig

@@ -1,2 +1 @@
 source src/drivers/emulation/qemu/Kconfig
-

src/drivers/i2c/tpm/Kconfig

@@ -11,4 +11,3 @@ config DRIVER_TPM_I2C_ADDR
 	hex "I2C TPM chip address"
 	default 2 # FIXME, workaround for Kconfig BS
 	depends on I2C_TPM
-

src/drivers/intel/fsp1_0/cache_as_ram.inc

@@ -174,4 +174,3 @@ CAR_init_params:
 CAR_init_stack:
 	.long  CAR_init_done
 	.long  CAR_init_params
-

src/drivers/intel/gma/int15.h

@@ -32,4 +32,3 @@ void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int
 #else
 static inline void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type) {}
 #endif
-

src/drivers/trident/Kconfig

@@ -1,2 +1 @@
 source src/drivers/trident/blade3d/Kconfig
-

src/drivers/xgi/common/vb_init.h

@@ -22,4 +22,3 @@
 extern unsigned char XGIInitNew(struct pci_dev *pdev);
 extern void XGIRegInit(struct vb_device_info *, unsigned long);
 #endif
-

src/drivers/xgi/common/vb_util.h

@@ -25,4 +25,3 @@ extern void xgifb_reg_or(unsigned long, u8, unsigned);
 extern void xgifb_reg_and(unsigned long, u8, unsigned);
 extern void xgifb_reg_and_or(unsigned long, u8, unsigned, unsigned);
 #endif
-

src/drivers/xgi/common/vgatypes.h

@@ -61,4 +61,3 @@ struct xgi_hw_device_info {
 /* Additional IOCTL for communication xgifb <> X driver        */
 /* If changing this, xgifb.h must also be changed (for xgifb) */
 #endif
-

src/drivers/xgi/common/vstruct.h

@@ -548,4 +548,3 @@ struct SiS_Private
 };
 
 #endif
-

src/include/cpu/amd/microcode.h

@@ -5,4 +5,3 @@ void update_microcode(u32 cpu_deviceid);
 void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id);
 
 #endif /* CPU_AMD_MICROCODE_H */
-

src/include/cpu/x86/name.h

@@ -23,4 +23,3 @@
 void fill_processor_name(char *processor_name);
 
 #endif
-

src/include/romstage_handoff.h

@@ -62,4 +62,3 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void)
 }
 
 #endif /* ROMSTAGE_HANDOFF_H */
-

src/mainboard/aaeon/pfm-540i_revb/devicetree.cb

@@ -71,4 +71,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-

src/mainboard/amd/db800/devicetree.cb

@@ -65,4 +65,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-

src/mainboard/amd/dbm690t/devicetree.cb

@@ -119,4 +119,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-

src/mainboard/amd/dinar/buildOpts.c

@@ -476,4 +476,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/dinar/devicetree.cb

@@ -106,4 +106,3 @@ chip northbridge/amd/agesa/family15/root_complex
 		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #domain
 end #northbridge/amd/agesa/family15/root_complex
-

src/mainboard/amd/inagua/Kconfig

@@ -80,4 +80,3 @@ config SB800_AHCI_ROM
 	default n
 
 endif # BOARD_AMD_INAGUA
-

src/mainboard/amd/inagua/buildOpts.c

@@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/inagua/devicetree.cb

@@ -94,4 +94,3 @@ chip northbridge/amd/agesa/family14/root_complex
 		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
 	end #domain
 end #northbridge/amd/agesa/family14/root_complex
-

src/mainboard/amd/lamar/acpi/si.asl

@@ -24,5 +24,3 @@
 			/* DBGO("\n") */
 		}
 	} /* End Scope SI */
-
-

src/mainboard/amd/norwich/devicetree.cb

@@ -38,4 +38,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-

src/mainboard/amd/olivehill/buildOpts.c

@@ -454,4 +454,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/olivehillplus/acpi/usb_oc.asl

@@ -38,4 +38,3 @@ Name(UOM6, 6)
 Name(UOM7, 2)
 Name(UOM8, 6)
 Name(UOM9, 6)
-

src/mainboard/amd/parmer/buildOpts.c

@@ -447,4 +447,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/persimmon/buildOpts.c

@@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/pistachio/acpi_tables.c

@@ -56,4 +56,3 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	return current;
 }
-

src/mainboard/amd/pistachio/devicetree.cb

@@ -78,4 +78,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-

src/mainboard/amd/rumba/devicetree.cb

@@ -18,4 +18,3 @@ chip northbridge/amd/gx2
       		end
     	end
 end
-

src/mainboard/amd/serengeti_cheetah/devicetree.cb

@@ -145,5 +145,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #domain
 end
-
-

src/mainboard/amd/serengeti_cheetah/readme_acpi.txt

@@ -27,4 +27,3 @@ use c to delele hex file
 yhlu
 
 09/18/2005
-

src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb

@@ -135,5 +135,3 @@ chip northbridge/amd/amdfam10/root_complex
 #	end #domain
 
 end
-
-

src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h

@@ -1,2 +1 @@
 unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp);
-

src/mainboard/amd/south_station/Kconfig

@@ -73,4 +73,3 @@ config VGA_BIOS_ID
 	default "1002,9806"
 
 endif # BOARD_AMD_SOUTHSTATION
-

src/mainboard/amd/south_station/buildOpts.c

@@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/south_station/devicetree.cb

@@ -109,4 +109,3 @@ chip northbridge/amd/agesa/family14/root_complex
                 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family14/root_complex
-

src/mainboard/amd/thatcher/buildOpts.c

@@ -447,4 +447,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/torpedo/buildOpts.c

@@ -318,4 +318,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/torpedo/devicetree.cb

@@ -87,4 +87,3 @@ chip northbridge/amd/agesa/family12/root_complex
                 end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family12/root_complex
-

src/mainboard/amd/union_station/Kconfig

@@ -72,4 +72,3 @@ config VGA_BIOS_ID
 	default "1002,9802"
 
 endif # BOARD_AMD_UNIONSTATION
-

src/mainboard/amd/union_station/buildOpts.c

@@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/amd/union_station/devicetree.cb

@@ -85,4 +85,3 @@ chip northbridge/amd/agesa/family14/root_complex
                 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family14/root_complex
-

src/mainboard/apple/macbook21/cmos.layout

@@ -134,5 +134,3 @@ enumerations
 checksums
 
 checksum 392 983 984
-
-

src/mainboard/apple/macbook21/mainboard.c

@@ -94,4 +94,3 @@ struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 	.final = mainboard_final,
 };
-

src/mainboard/arima/hdama/devicetree.cb

@@ -183,4 +183,3 @@ chip northbridge/amd/amdk8/root_complex
 		end  # chip northbridge/amd/amdk8
 	end
 end
-

src/mainboard/artecgroup/dbe61/devicetree.cb

@@ -39,4 +39,3 @@ chip northbridge/amd/lx
 	end
 
 end
-

src/mainboard/asrock/939a785gmh/devicetree.cb

@@ -129,4 +129,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-

src/mainboard/asrock/e350m1/Kconfig

@@ -66,4 +66,3 @@ config VGA_BIOS_ID
 	default "1002,9802"
 
 endif # BOARD_ASROCK_E350M1
-

src/mainboard/asrock/e350m1/buildOpts.c

@@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/asrock/imb-a180/buildOpts.c

@@ -454,4 +454,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/asus/f2a85-m/buildOpts.c

@@ -446,4 +446,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
   */
   PSO_END
 };
-

src/mainboard/asus/f2a85-m_le/buildOpts.c

@@ -447,4 +447,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
   */
   PSO_END
 };
-

src/mainboard/asus/mew-vm/devicetree.cb

@@ -49,4 +49,3 @@ chip northbridge/intel/i82810
 	chip cpu/intel/socket_PGA370
 	end
 end
-

src/mainboard/bap/ode_e20XX/buildOpts.c

@@ -463,4 +463,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/biostar/am1ml/acpi/sata.asl

@@ -146,4 +146,3 @@ Scope(\_GPE) {
 		}
 	}
 }
-

src/mainboard/biostar/am1ml/buildOpts.c

@@ -454,4 +454,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 #include "mm.h"
 #include "mn.h"
-

src/mainboard/broadcom/blast/devicetree.cb

@@ -120,4 +120,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #domain
 end
-

src/mainboard/cubietech/cubieboard/board_info.txt

@@ -1,2 +1 @@
 Category: sbc
-

src/mainboard/cubietech/cubieboard/memlayout.ld

@@ -33,4 +33,3 @@ SECTIONS
 	RAMSTAGE(0x40000000, 16M)
 	ROMSTAGE(0x41000000, 108K)
 }
-