src/mainboard to src/security: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/emulation/qemu-armv7/memlayout.ld

@@ -18,7 +18,7 @@
  * with -bios option which neatly puts coreboot into flash and so payloads
  * can find CBFS and we don't risk overwriting CBFS.
  *
- * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash
+ * Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash
  * and -bios was unusable as $pc pointed to 0 which was zero-filled as a
  * workaround we suggested using -kernel but this still had all the issues
  * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends

src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h

@@ -2,7 +2,7 @@
 
 /*
  * These are the qemu firmware config interface defines and structs.
- * Copied over from qemu soure tree,
+ * Copied over from qemu source tree,
  * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly.
  */
 #ifndef FW_CFG_IF_H

src/mainboard/emulation/qemu-q35/bootblock.c

@@ -16,7 +16,7 @@ static void bootblock_northbridge_init(void)
 	 * MCFG. This code also assumes that bootblock_northbridge_init() is
 	 * the first thing called in the non-asm boot block code. The final
 	 * assumption is that no assembly code is using the
-	 * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
+	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
 	 * 4GiB.