src/mainboard to src/security: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/amd/bilby/devicetree.cb

@@ -127,7 +127,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_OFF"
 	register "gpp_clk_config[1]" = "GPP_CLK_OFF"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

src/mainboard/amd/mandolin/variants/cereme/devicetree.cb

@@ -118,7 +118,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb

@@ -118,7 +118,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"