erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Remove DEFAULT_PCIEXBAR alias

Browse source 
The other DEFAULT_ entries are just immediate
constants.

Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-03-05 07:54:28 +02:00 • committed by Nico Huber
commit 503d3247e4
26 changed files with 23 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/northbridge/intel/gm45/acpi/gm45.asl
View file

@ -40,7 +40,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

2
src/northbridge/intel/gm45/gm45.h
View file

@ -195,8 +195,6 @@ enum {
#define DEFAULT_EPBAR 0xfed19000
#define DEFAULT_HECIBAR ((u8 *)0xfed1a000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000

2
src/northbridge/intel/haswell/acpi/haswell.asl
View file

@ -28,7 +28,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/haswell/haswell.h
View file

@ -26,7 +26,6 @@
#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#ifndef __ACPI__
#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */

2
src/northbridge/intel/i945/acpi/i945.asl
View file

@ -55,7 +55,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/i945/i945.h
View file

@ -17,7 +17,6 @@
#define NORTHBRIDGE_INTEL_I945_H
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_X60BAR 0xfed13000
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */

2
src/northbridge/intel/nehalem/acpi/nehalem.asl
View file

@ -28,7 +28,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

2
src/northbridge/intel/nehalem/bootblock.c
View file

@ -15,6 +15,6 @@
static void bootblock_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1);
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1);
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0);
}

3
src/northbridge/intel/nehalem/nehalem.h
View file

@ -52,8 +52,6 @@ typedef struct {
#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
@ -128,7 +126,6 @@ typedef struct {
#define IED_SIZE 0x400000
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */

2
src/northbridge/intel/pineview/acpi/pineview.asl
View file

@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */

3
src/northbridge/intel/pineview/iomap.h
View file

@ -17,9 +17,6 @@
#ifndef PINEVIEW_IOMAP_H
#define PINEVIEW_IOMAP_H
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */

2
src/northbridge/intel/sandybridge/acpi/sandybridge.asl
View file

@ -30,7 +30,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/sandybridge/sandybridge.h
View file

@ -39,7 +39,6 @@
#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */

2
src/northbridge/intel/x4x/acpi/x4x.asl
View file

@ -29,7 +29,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

3
src/northbridge/intel/x4x/iomap.h
View file

@ -17,9 +17,6 @@
#ifndef X4X_IOMAP_H
#define X4X_IOMAP_H
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */