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pit: When turning on caching, cache the SRAM as well.

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The stack is still in SRAM, and this improves performance substantially.

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BUG=chrome-os-partner:19420
TEST=Built and booted on pit.
BRANCH=None

Change-Id: Iaaecd7da2b21391d2f9657ec4673654843b9eff8
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65779
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-08-13 16:30:12 -07:00 • committed by ChromeBot
commit 50113ae2a4
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/pit/mainboard.c
View file

@ -44,6 +44,8 @@
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
#define SRAM_START (0x02020000 >> 20)
#define SRAM_SIZE 1
static struct edid edid = {
.ha = 1366,
@ -447,6 +449,7 @@ static void mainboard_enable(device_t dev)
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_invalidate_all();
dcache_mmu_enable();