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Unify use of post_code

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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>                                                                                                         
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Alexandru Gagniuc 2011-04-11 20:17:22 +00:00 • committed by Stefan Reinauer
commit 5005bb06c1
40 changed files with 408 additions and 262 deletions
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5
src/cpu/intel/car/cache_as_ram.inc
View file

@ -24,6 +24,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/x86/post_code.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
@ -364,7 +365,7 @@ lout:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -375,7 +376,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/intel/model_106cx/cache_as_ram.inc
View file

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/intel/model_6ex/cache_as_ram.inc
View file

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/intel/model_6fx/cache_as_ram.inc
View file

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@ -243,7 +244,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -254,7 +255,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt