From 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 18 Aug 2014 13:18:58 -0700 Subject: [PATCH] tegra132: separate/refactor clock enable/reset code Added distinct functions for clock_enable and clock_clear_reset, and rewrote clock_enable_clear_reset() to use them. Useful when unpowergating SOR partition, for instance, where we need to enable a bunch of periph clocks, unclamp SOR, then take all of those periphs out of reset. BUG=none BRANCH=none TEST=none, built rush/ryu OK. Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32 Signed-off-by: Tom Warren Reviewed-on: https://chromium-review.googlesource.com/212916 Reviewed-by: Aaron Durbin --- src/soc/nvidia/tegra132/clock.c | 18 ++++++++++++++---- src/soc/nvidia/tegra132/include/soc/clock.h | 2 ++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index df66ded3e4..14307da6b3 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -585,7 +585,7 @@ void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, writel(val, rst_dev_clr_reg); } -void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +void clock_enable(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) { if (l) writel(l, &clk_rst->clk_enb_l_set); if (h) writel(h, &clk_rst->clk_enb_h_set); @@ -593,10 +593,10 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) if (v) writel(v, &clk_rst->clk_enb_v_set); if (w) writel(w, &clk_rst->clk_enb_w_set); if (x) writel(x, &clk_rst->clk_enb_x_set); +} - /* Give clocks time to stabilize. */ - udelay(IO_STABILIZATION_DELAY); - +void clock_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +{ if (l) writel(l, &clk_rst->rst_dev_l_clr); if (h) writel(h, &clk_rst->rst_dev_h_clr); if (u) writel(u, &clk_rst->rst_dev_u_clr); @@ -605,6 +605,16 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) if (x) writel(x, &clk_rst->rst_dev_x_clr); } +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) +{ + clock_enable(l, h, u, v, w, x); + + /* Give clocks time to stabilize. */ + udelay(IO_STABILIZATION_DELAY); + + clock_clear_reset(l, h, u, v, w, x); +} + void clock_reset_l(u32 bit) { writel(bit, &clk_rst->rst_dev_l_set); diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h index 6f98e3c618..494f28d4db 100644 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -292,6 +292,8 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 same_freq); void clock_cpu0_config(void); void clock_halt_avp(void); +void clock_enable(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); +void clock_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg); void clock_reset_l(u32 l);