UPSTREAM: src/cpu: Capitalize ROM and RAM

BUG=None
BRANCH=None
TEST=None

Change-Id: Ice2c8033f60af8c2471cc00f57a9dc83dbd69892
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/366260
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

src/cpu/amd/agesa/cache_as_ram.inc

@@ -80,7 +80,7 @@ cache_as_ram_setup:
   movl    $0xc00000e3, 0x18(%edi)
   movl    %eax, 0x1c(%edi)
 
-  # load rom based identity mapped page tables
+  # load ROM based identity mapped page tables
   mov     %ecx, %eax
   mov     %eax, %cr3
 

src/cpu/amd/car/post_cache_as_ram.c

@@ -166,7 +166,7 @@ void post_cache_as_ram(void)
 
 void cache_as_ram_new_stack (void)
 {
-	print_car_debug("Disabling cache as ram now\n");
+	print_car_debug("Disabling cache as RAM now\n");
 	disable_cache_as_ram_bsp();
 
 	disable_cache();

src/cpu/amd/geode_gx2/cache_as_ram.inc

@@ -171,7 +171,7 @@ done_cache_as_ram_main:
 	pop    %esi
 	pop    %edi
 
-	/* Clear the cache out to ram */
+	/* Clear the cache out to RAM */
 	wbinvd
 	/* re-enable the cache */
 	movl    %cr0, %eax

src/cpu/amd/geode_lx/cache_as_ram.inc

@@ -198,7 +198,7 @@ done_cache_as_ram_main:
 	pop    %esi
 	pop    %edi
 
-	/* Clear the cache out to ram */
+	/* Clear the cache out to RAM */
 	wbinvd
 	/* re-enable the cache */
 	movl    %cr0, %eax

src/cpu/amd/pi/cache_as_ram.inc

@@ -81,7 +81,7 @@ cache_as_ram_setup:
   movl    $0xc00000e3, 0x18(%edi)
   movl    %eax, 0x1c(%edi)
 
-  # load rom based identity mapped page tables
+  # load ROM based identity mapped page tables
   mov     %ecx, %eax
   mov     %eax, %cr3