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arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE

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If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.

This also adds board reset for failing to load postcar
from stage cache.

Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-12-18 19:40:48 +02:00
commit 4f14cd8a39
11 changed files with 15 additions and 65 deletions
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configs/config.google_meep_cros
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@ -2,7 +2,6 @@ CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_MEEP=y
CONFIG_PAYLOAD_NONE=y
CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SMM=y
CONFIG_USE_BLOBS=y