From 4e7f0e8ae1138e478ae7106d54719cf05e13b402 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 5 Feb 2014 14:55:26 -0600 Subject: [PATCH] baytrail: combine SPI configuration in romstage There were previously two functions manipulating the SPI controller state: open_up_spi() and spi_init(). Combine the contents of open_up_spi() with spi_init(). Add the appropriate defintions in the SPI header. BUG=chrome-os-partner:24624 BRANCH=baytrail TEST=Built and booted. BCR and SCS register the same, as expected. Change-Id: I108a3d3f55fa63e52960b6d42adca122547cab47 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/185140 Reviewed-by: Duncan Laurie --- src/soc/intel/baytrail/baytrail/spi.h | 5 ++++ src/soc/intel/baytrail/romstage/romstage.c | 27 ++++++++++------------ 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/spi.h b/src/soc/intel/baytrail/baytrail/spi.h index abe9e142bc..904e7a1d08 100644 --- a/src/soc/intel/baytrail/baytrail/spi.h +++ b/src/soc/intel/baytrail/baytrail/spi.h @@ -21,11 +21,16 @@ #define _BAYTRAIL_SPI_H_ /* These registers live behind SPI_BASE_ADDRESS. */ +#define SCS 0xf8 +# define SMIWPEN (0x1 << 7) #define BCR 0xfc +# define EISS (0x1 << 5) # define SRC_MASK (0x3 << 2) # define SRC_CACHE_NO_PREFETCH (0x0 << 2) # define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2) # define SRC_CACHE_PREFETCH (0x2 << 2) +# define BCR_LE (0x1 << 1) +# define BCR_WPD (0x1 << 0) #endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 80ce6f8327..26a9e2777a 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -84,9 +84,19 @@ static void program_base_addresses(void) static void spi_init(void) { + const unsigned long scs = SPI_BASE_ADDRESS + SCS; const unsigned long bcr = SPI_BASE_ADDRESS + BCR; - /* Enable caching and prefetching in the SPI controller. */ - write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); } static inline void mark_ts(struct romstage_params *rp, uint64_t ts) @@ -254,21 +264,8 @@ void romstage_common(struct romstage_params *params) timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } -static void open_up_spi(void) -{ - const uintptr_t sbase = SPI_BASE_ADDRESS; - - /* Disable generating SMI when setting WPD bit. */ - write32(sbase + 0xf8, read32(sbase + 0xf8) & ~(1 << 7)); - /* Disable the SMM-only BIOS write and set WPD bit. */ - write32(sbase + 0xfc, 1 | (read32(sbase + 0xfc) & ~(1 << 5))); -} - void asmlinkage romstage_after_car(void) { - /* Allow BIOS to program SPI part. */ - open_up_spi(); - timestamp_add_now(TS_END_ROMSTAGE); /* Run vboot verification if configured. */